From 2a58d3c27b45ca9d0d9dc2136377b7a41b9ed82d Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Mon, 22 Feb 2016 12:35:49 -0500 Subject: gpu: nvgpu: improve channel interleave support Previously, only "high" priority bare channels were interleaved between all other bare channels and TSGs. This patch decouples priority from interleaving and introduces 3 levels for interleaving a bare channel or TSG: high, medium, and low. The levels define the number of times a channel or TSG will appear on a runlist (see nvgpu.h for details). By default, all bare channels and TSGs are set to interleave level low. Userspace can then request the interleave level to be increased via the CHANNEL_SET_RUNLIST_INTERLEAVE ioctl (TSG-specific ioctl will be added later). As timeslice settings will soon be coming from userspace, the default timeslice for "high" priority channels has been restored. JIRA VFND-1302 Bug 1729664 Change-Id: I178bc1cecda23f5002fec6d791e6dcaedfa05c0c Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/1014962 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index ee4e7328..0979bf2b 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -31,7 +31,6 @@ struct fifo_runlist_info_gk20a { unsigned long *active_channels; unsigned long *active_tsgs; - unsigned long *high_prio_channels; /* Each engine has its own SW and HW runlist buffer.*/ struct mem_desc mem[MAX_RUNLIST_BUFFERS]; u32 cur_buffer; @@ -184,8 +183,6 @@ void fifo_gk20a_finish_mmu_fault_handling(struct gk20a *g, int gk20a_fifo_wait_engine_idle(struct gk20a *g); u32 gk20a_fifo_engine_interrupt_mask(struct gk20a *g); u32 gk20a_fifo_get_pbdma_signature(struct gk20a *g); -int gk20a_fifo_set_channel_priority(struct gk20a *g, u32 runlist_id, - u32 hw_chid, bool interleave); u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, int *__id, bool *__is_tsg); bool gk20a_fifo_set_ctx_mmu_error_tsg(struct gk20a *g, @@ -198,4 +195,9 @@ struct channel_gk20a *gk20a_fifo_channel_from_hw_chid(struct gk20a *g, u32 hw_chid); void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg); +int gk20a_fifo_set_runlist_interleave(struct gk20a *g, + u32 id, + bool is_tsg, + u32 runlist_id, + u32 new_level); #endif /*__GR_GK20A_H__*/ -- cgit v1.2.2