From ab401c70682c98adae6f3c5c7225fdc8e1294fc7 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Wed, 22 Mar 2017 16:57:56 -0700 Subject: gpu: nvgpu: fix running condition on fifo isr The fifo interrupt path was reading the PBDMA interrupt status after clearing interrupts and this could lead to a situation in which the host may have advanced to another channel, leading to the recovery code resetting the wrong channel. Bug 200278729 JIRA: EVLR-1036 Change-Id: I392423d1eaa8d23acf88454bf113c015e649e13d Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1326461 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 60190521..8f7a2e22 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -2289,6 +2289,8 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev, { u32 pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id)); u32 pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); + u32 status = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); + u32 handled = 0; u32 error_notifier = NVGPU_CHANNEL_PBDMA_ERROR; bool reset = false; @@ -2374,7 +2376,6 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev, if (reset) { /* Remove the channel from runlist */ - u32 status = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); u32 id = fifo_pbdma_status_id_v(status); if (fifo_pbdma_status_id_type_v(status) == fifo_pbdma_status_id_type_chid_v()) { -- cgit v1.2.2