From 89aecd1202b49727e940069f2a6feb5c3cf4c927 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 29 Jun 2016 16:06:39 +0530 Subject: gpu: nvgpu: Add nvgpu infra to allow kernel to create privileged CE channels Added interface to allow kernel to create privileged CE channels for page migration and clearing support between sysmem and videmem. JIRA DNVGPU-53 Change-Id: I3e18d18403809c9e64fa45d40b6c4e3844992506 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1173085 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 5133f86a..3dd7cb02 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -165,6 +165,33 @@ u32 gk20a_fifo_get_all_ce_engine_reset_mask(struct gk20a *g) return reset_mask; } +u32 gk20a_fifo_get_fast_ce_runlist_id(struct gk20a *g) +{ + u32 ce_runlist_id = gk20a_fifo_get_gr_runlist_id(g); + u32 engine_enum = ENGINE_INVAL_GK20A; + struct fifo_gk20a *f = NULL; + u32 engine_id_idx; + struct fifo_engine_info_gk20a *engine_info; + u32 active_engine_id = 0; + + if (!g) + return ce_runlist_id; + + f = &g->fifo; + + for (engine_id_idx = 0; engine_id_idx < f->num_engines; ++engine_id_idx) { + active_engine_id = f->active_engines_list[engine_id_idx]; + engine_info = &f->engine_info[active_engine_id]; + engine_enum = engine_info->engine_enum; + + /* selecet last available ASYNC_CE if available */ + if (engine_enum == ENGINE_ASYNC_CE_GK20A) + ce_runlist_id = engine_info->runlist_id; + } + + return ce_runlist_id; +} + u32 gk20a_fifo_get_gr_runlist_id(struct gk20a *g) { u32 gr_engine_cnt = 0; -- cgit v1.2.2