From 1c40d09c4c9c011c1318c328c0b4b6b17d1f537e Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 19 Aug 2015 14:27:51 -0700 Subject: gpu: nvgpu: Add support for FECS ctxsw tracing bug 1648908 This commit adds support for FECS ctxsw tracing. Code is compiled conditionnaly under CONFIG_GK20_CTXSW_TRACE. This feature requires an updated FECS ucode that writes one record to a ring buffer on each context switch. On RM/Kernel side, the GPU driver reads records from the master ring buffer and generates trace entries into a user-facing VM ring buffer. For each record in the master ring buffer, RM/Kernel has to retrieve the vmid+pid of the user process that submitted related work. Features currently implemented: - master ring buffer allocation - debugfs to dump master ring buffer - FECS record per context switch (with both current and new contexts) - dedicated device for ctxsw tracing (access to VM ring buffer) - SOF generation (and access to PTIMER) - VM ring buffer allocation, and reconfiguration - enable/disable tracing at user level - event-based trace filtering - context_ptr to vmid+pid mapping - read system call for ctxsw dev - mmap system call for ctxsw dev (direct access to VM ring buffer) - poll system call for ctxsw dev - save/restore register on ELPG/CG6 - separate user ring from FECS ring handling Features requiring ucode changes: - enable/disable tracing at FECS level - actual busy time on engine (bug 1642354) - master ring buffer threshold interrupt (P1) - API for GPU to CPU timestamp conversion (P1) - vmid/pid/uid based filtering (P1) Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1022737 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 661c2c38..029a713f 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -25,6 +25,7 @@ #include "gk20a.h" #include "debug_gk20a.h" +#include "ctxsw_trace_gk20a.h" #include "semaphore_gk20a.h" #include "hw_fifo_gk20a.h" #include "hw_pbdma_gk20a.h" @@ -776,13 +777,17 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) if (engine_id == top_device_info_type_enum_graphics_v()) { if (support_gk20a_pmu(g->dev) && g->elpg_enabled) gk20a_pmu_disable_elpg(g); - /*HALT_PIPELINE method, halt GR engine*/ - if (gr_gk20a_halt_pipe(g)) - gk20a_err(dev_from_gk20a(g), - "failed to HALT gr pipe"); - /* resetting engine using mc_enable_r() is not - enough, we do full init sequence */ - gk20a_gr_reset(g); + /*HALT_PIPELINE method, halt GR engine*/ + if (gr_gk20a_halt_pipe(g)) + gk20a_err(dev_from_gk20a(g), "failed to HALT gr pipe"); + /* resetting engine will alter read/write index. + * need to flush circular buffer before re-enabling FECS. + */ + if (g->ops.fecs_trace.reset) + g->ops.fecs_trace.reset(g); + /* resetting engine using mc_enable_r() is not + enough, we do full init sequence */ + gk20a_gr_reset(g); if (support_gk20a_pmu(g->dev) && g->elpg_enabled) gk20a_pmu_enable_elpg(g); } -- cgit v1.2.2