From 17aeea4a2ffa23fc9dbcdc84cda747fe5a025131 Mon Sep 17 00:00:00 2001 From: Srirangan Date: Thu, 2 Aug 2018 14:15:54 +0530 Subject: gpu: nvgpu: gk20a: Fix MISRA 15.6 violations This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/gk20a/ JIRA NVGPU-989 Change-Id: I2f422e9bc2b03229f4d2c3198613169ce5e7f3ee Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1791019 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/fifo_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 93ef211e..23e22c21 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -907,8 +907,9 @@ int gk20a_init_fifo_setup_sw_common(struct gk20a *g) memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32))); /* pbdma map needs to be in place before calling engine info init */ - for (i = 0; i < f->num_pbdma; ++i) + for (i = 0; i < f->num_pbdma; ++i) { f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i)); + } g->ops.fifo.init_engine_info(f); @@ -2496,9 +2497,10 @@ unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, f->intr.pbdma.restartable_0) & pbdma_intr_0) { pbdma_intr_err = (unsigned long)pbdma_intr_0; - for_each_set_bit(bit, &pbdma_intr_err, 32) + for_each_set_bit(bit, &pbdma_intr_err, 32) { nvgpu_err(g, "PBDMA intr %s Error", pbdma_intr_fault_type_desc[bit]); + } nvgpu_err(g, "pbdma_intr_0(%d):0x%08x PBH: %08x " @@ -2851,8 +2853,9 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) return 0; /* we have no idea which runlist we are using. lock all */ - for (i = 0; i < g->fifo.max_runlists; i++) + for (i = 0; i < g->fifo.max_runlists; i++) { nvgpu_mutex_acquire(&f->runlist_info[i].runlist_lock); + } mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -2861,8 +2864,9 @@ int gk20a_fifo_preempt_channel(struct gk20a *g, u32 chid) if (!mutex_ret) nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - for (i = 0; i < g->fifo.max_runlists; i++) + for (i = 0; i < g->fifo.max_runlists; i++) { nvgpu_mutex_release(&f->runlist_info[i].runlist_lock); + } if (ret) { if (nvgpu_platform_is_silicon(g)) { @@ -2891,8 +2895,9 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) return 0; /* we have no idea which runlist we are using. lock all */ - for (i = 0; i < g->fifo.max_runlists; i++) + for (i = 0; i < g->fifo.max_runlists; i++) { nvgpu_mutex_acquire(&f->runlist_info[i].runlist_lock); + } mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); @@ -2901,8 +2906,9 @@ int gk20a_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) if (!mutex_ret) nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - for (i = 0; i < g->fifo.max_runlists; i++) + for (i = 0; i < g->fifo.max_runlists; i++) { nvgpu_mutex_release(&f->runlist_info[i].runlist_lock); + } if (ret) { if (nvgpu_platform_is_silicon(g)) { -- cgit v1.2.2