From 88c6d2fb21ad2f3f1be09c2014560aa22b27ba98 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Fri, 27 Jun 2014 14:50:31 +0530 Subject: gpu:nvgpu:fix powergate disabling order ELPG has to disabled before we write to clock gating registers If ELPG is engaged during clock gating register write it will cause error in ELPG engine Bug 200013495 Bug 200014542 Change-Id: I57d1c59fc9311686829d898faddc90149df4cb46 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/432117 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Supriya Sharatkumar GVS: Gerrit_Virtual_Submit Reviewed-by: Mitch Luban --- drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 7a1140f9..8cb1d0a5 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c @@ -576,6 +576,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, if (err) return -EPERM; + /*do elpg disable before clock gating */ + gk20a_pmu_disable_elpg(g); g->ops.clock_gating.slcg_gr_load_gating_prod(g, false); g->ops.clock_gating.slcg_perf_load_gating_prod(g, @@ -586,7 +588,6 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A); gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A); - gk20a_pmu_disable_elpg(g); } dbg_s->is_pg_disabled = true; -- cgit v1.2.2