From 3ba374a5d94f8c2067731155afaf79f03e6c390c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Mar 2017 07:44:03 -0700 Subject: gpu: nvgpu: gk20a: Use new error macro gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: Ia51f36d94c5ce57a5a0ab83b3c83a6bce09e2d5c Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1331694 Reviewed-by: svccoveritychecker Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/clk_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 38d4b555..443cd5e1 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c @@ -24,6 +24,8 @@ #include "gk20a.h" +#include + #include #include @@ -251,7 +253,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r()); if (ramp_timeout <= 0) { - gk20a_err(dev_from_gk20a(g), "gpcpll dynamic ramp timeout"); + nvgpu_err(g, "gpcpll dynamic ramp timeout"); return -ETIMEDOUT; } return 0; @@ -439,7 +441,7 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) ref = clk_get_parent(clk_get_parent(clk->tegra_clk)); if (IS_ERR(ref)) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "failed to get GPCPLL reference clock"); err = -EINVAL; goto fail; @@ -449,7 +451,7 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) clk->gpc_pll.id = GK20A_GPC_PLL; clk->gpc_pll.clk_in = ref_rate / KHZ; if (clk->gpc_pll.clk_in == 0) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "GPCPLL reference clock is zero"); err = -EINVAL; goto fail; @@ -508,7 +510,7 @@ static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq) /* gpc_pll.freq is changed to new value here */ if (clk_config_pll(clk, &clk->gpc_pll, &gpc_pll_params, &freq, true)) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "failed to set pll target for %d", freq); return -EINVAL; } @@ -536,8 +538,7 @@ static int set_pll_freq(struct gk20a *g, u32 freq, u32 old_freq) /* Just report error but not restore PLL since dvfs could already change voltage even when it returns error. */ if (err) - gk20a_err(dev_from_gk20a(g), - "failed to set pll to %d", freq); + nvgpu_err(g, "failed to set pll to %d", freq); return err; } -- cgit v1.2.2