From 3058fb2b960cf1da53fd25c5c8d286d60560615e Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Mon, 14 Jul 2014 17:01:31 -0700 Subject: gpu: nvgpu: Use 1kHz resolution for GPCPLL programming Used 1kHz resolution (instead of 1 MHz) for GPCPLL programming: limits specifications, calculating GPCPLL settings, storing target frequency values, and proving output from debug monitor. Updated comments in clock header to properly reflect frequency units. Bug 1450787 Change-Id: Ica58f794b82522288f2883c40626d82dbd794902 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/437943 Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Yu-Huan Hsu --- drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/clk_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 151a332b..33d81bd4 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c @@ -34,12 +34,12 @@ /* from vbios PLL info table */ struct pll_parms gpc_pll_params = { - 144, 2064, /* freq */ - 1000, 2064, /* vco */ - 12, 38, /* u */ - 1, 255, /* M */ - 8, 255, /* N */ - 1, 32, /* PL */ + 144000, 2064000, /* freq */ + 1000000, 2064000, /* vco */ + 12000, 38000, /* u */ + 1, 255, /* M */ + 8, 255, /* N */ + 1, 32, /* PL */ }; static int num_gpu_cooling_freq; @@ -467,7 +467,7 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) clk->pll_delay = 300; /* usec */ clk->gpc_pll.id = GK20A_GPC_PLL; - clk->gpc_pll.clk_in = ref_rate / 1000000; /* MHz */ + clk->gpc_pll.clk_in = ref_rate / KHZ; /* Decide initial frequency */ if (!initialized) { @@ -777,7 +777,7 @@ static int pll_reg_show(struct seq_file *s, void *data) pl = trim_sys_gpcpll_coeff_pldiv_v(reg); f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div[pl]); seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl); - seq_printf(s, " : pll_f(gpu_f) = %u(%u) MHz\n", f, f/2); + seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2); mutex_unlock(&g->clk.clk_mutex); return 0; } @@ -801,7 +801,7 @@ static int monitor_get(void *data, u64 *val) int err; u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */ - u32 clkin = clk->gpc_pll.clk_in; + u64 freq = clk->gpc_pll.clk_in; u32 count1, count2; err = gk20a_busy(g->dev); @@ -824,7 +824,10 @@ static int monitor_get(void *data, u64 *val) count1 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); udelay(100); count2 = gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cnt_r(0)); - *val = (u64)(trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2) * clkin / ncycle); + freq *= trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(count2); + do_div(freq, ncycle); + *val = freq; + gk20a_idle(g->dev); if (count1 != count2) -- cgit v1.2.2