From ab93322b25c9dd6058fac6523f41571d77eeaeb9 Mon Sep 17 00:00:00 2001 From: sujeet baranwal Date: Mon, 28 Sep 2015 15:26:23 -0700 Subject: gpu: nvgpu: Add CDE bits in FECS header In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B aligned, otherwise causes a HW deadlock. Gpu driver makes changes in FECS header which FECS uses to configure the T1 promotions to aligned 128B accesses. Bug 200096226 Change-Id: I8a8deaf6fb91f4bbceacd491db7eb6f7bca5001b Signed-off-by: sujeet baranwal Reviewed-by: Terje Bergstrom Signed-off-by: sujeet baranwal Reviewed-on: http://git-master/r/804625 Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gk20a/channel_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 70930291..9d74b412 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -100,6 +100,7 @@ struct channel_gk20a { bool bound; bool first_init; bool vpr; + bool cde; pid_t pid; struct mutex ioctl_lock; -- cgit v1.2.2