From e02d14e7542aed80c8f37c12a1d5df127146fbd3 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Wed, 4 Oct 2017 10:44:40 -0700 Subject: gpu: nvgpu: ce: tsg and large vidmem support Some GPUs require all channels to be on TSG and also have larger than 4GB vidmem sizes which were not supported on the previous CE2 code. This change creates a new property to track if the copy engine needs to encapsulate its kernel context on tsg and also modifies the copy engine code to support much larger copies without dramatically increasing the PB size. JIRA: EVLR-1990 Change-Id: Ieb4acba0c787eb96cb9c7cd97f884d2119d445aa Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1573216 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: Terje Bergstrom Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel --- drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/ce2_gk20a.h') diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index f1f9e260..1dad8952 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h @@ -36,8 +36,8 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); #define NVGPU_CE_LOWER_ADDRESS_OFFSET_MASK 0xffffffff #define NVGPU_CE_UPPER_ADDRESS_OFFSET_MASK 0xff -#define NVGPU_CE_COMMAND_BUF_SIZE 4096 -#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 128 +#define NVGPU_CE_COMMAND_BUF_SIZE 8192 +#define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_PER_KICKOFF 256 #define NVGPU_CE_MAX_COMMAND_BUFF_SIZE_FOR_TRACING 8 typedef void (*ce_event_callback)(u32 ce_ctx_id, u32 ce_event_flag); @@ -108,6 +108,9 @@ struct gk20a_gpu_ctx { int gpu_ctx_state; ce_event_callback user_event_callback; + /* tsg related data */ + struct tsg_gk20a *tsg; + /* channel related data */ struct channel_gk20a *ch; struct vm_gk20a *vm; -- cgit v1.2.2