From 07f6739285140d7c5335ddcb8996450966bfc175 Mon Sep 17 00:00:00 2001 From: Scott Long Date: Wed, 8 Aug 2018 18:30:09 -0700 Subject: gpu: nvgpu: switch gk20a nonstall ops to #defines Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops enums by replacing them with with corresponding #defines. Because these values can be used in expressions that require unsigned values (e.g. bitwise OR) we cannot use enums. The g->ce2.isr_nonstall() function was previously returning an int that was a combination of gk20a_nonstall_ops enum bits which led to the violations. JIRA NVGPU-650 Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406 Signed-off-by: Scott Long Reviewed-on: https://git-master.nvidia.com/r/1796242 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gk20a/ce2_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 5aae0613..0248b0ca 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -88,9 +88,9 @@ void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base) return; } -int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +u32 gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { - int ops = 0; + u32 ops = 0; u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); nvgpu_log(g, gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); @@ -98,8 +98,8 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) { gk20a_writel(g, ce2_intr_status_r(), ce2_nonblockpipe_isr(g, ce2_intr)); - ops |= (gk20a_nonstall_ops_wakeup_semaphore | - gk20a_nonstall_ops_post_events); + ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE | + GK20A_NONSTALL_OPS_POST_EVENTS); } return ops; } -- cgit v1.2.2