From ae04f394cf9a82a762a7152747a6bba5be6f5f53 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 19 Apr 2018 07:14:28 -0700 Subject: gpu: nvgpu: add HAL to set ppriv timeouts Add new HAL gops.bus.set_ppriv_timeout_settings() to set platform specific ppriv timeouts Set this HAL for all supported GPUs for now Jira NVGPUT-35 Change-Id: I88b438a7bf381d0216e0947a16cd267461d0e8d7 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1699314 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/gpu/nvgpu/gk20a/bus_gk20a.c') diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index 81a5facc..ab75e8d7 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c @@ -34,6 +34,9 @@ #include #include #include +#include +#include +#include void gk20a_bus_init_hw(struct gk20a *g) { @@ -172,3 +175,14 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) return 0; } + +void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g) +{ + /* + * Bug 1340570: increase the clock timeout to avoid potential + * operation failure at high gpcclk rate. Default values are 0x400. + */ + nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); + nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); + nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800); +} -- cgit v1.2.2