From b17d9708c9e9930778de43de1edf1385acb13ebd Mon Sep 17 00:00:00 2001 From: Vijayakumar Subbu Date: Wed, 27 Jul 2016 22:29:15 -0700 Subject: gpu: nvgpu: Add dGPU clocks support JIRA DNVGPU-45 Change-Id: I237ce81e31b036c05c82d46eea8694ffe1c2e3df Signed-off-by: Mahantesh Kumbar Signed-off-by: Vijayakumar Subbu Reviewed-on: http://git-master/r/1205849 (cherry picked from commit 9a4006f76b75a8ad525e7aa5ad1f609aaae49126) Reviewed-on: http://git-master/r/1227256 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/ctrl/ctrlboardobj.h | 81 ++++++++++++++++++ drivers/gpu/nvgpu/ctrl/ctrlclk.h | 153 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | 88 +++++++++++++++++++ drivers/gpu/nvgpu/ctrl/ctrlperf.h | 32 +++++++ drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 40 +++++++++ 5 files changed, 394 insertions(+) create mode 100644 drivers/gpu/nvgpu/ctrl/ctrlboardobj.h create mode 100644 drivers/gpu/nvgpu/ctrl/ctrlclk.h create mode 100644 drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h create mode 100644 drivers/gpu/nvgpu/ctrl/ctrlperf.h create mode 100644 drivers/gpu/nvgpu/ctrl/ctrlvolt.h (limited to 'drivers/gpu/nvgpu/ctrl') diff --git a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h new file mode 100644 index 00000000..3d9599a6 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ctrlboardobj_h_ +#define _ctrlboardobj_h_ + +struct ctrl_boardobj { + u8 type; +}; + +#define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00 +#define CTRL_BOARDOBJGRP_TYPE_E32 0x01 +#define CTRL_BOARDOBJGRP_TYPE_E255 0x02 + +#define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32 + +#define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255 + +#define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS + +#define CTRL_BOARDOBJ_IDX_INVALID 255 + +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32 + +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ + ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) + +#define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_OFFSET(_bit) \ + ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) + +#define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ + (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1) + 1) + + +#define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1 +#define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ + (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ + CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE) + +struct ctrl_boardobjgrp_mask { + u32 data[1]; +}; + +struct ctrl_boardobjgrp_mask_e32 { + struct ctrl_boardobjgrp_mask super; +}; + +struct ctrl_boardobjgrp_mask_e255 { + struct ctrl_boardobjgrp_mask super; + u32 data_e255[7]; +}; + +struct ctrl_boardobjgrp_super { + struct ctrl_boardobjgrp_mask obj_mask; +}; + +struct ctrl_boardobjgrp_e32 { + struct ctrl_boardobjgrp_mask_e32 obj_mask; +}; + +struct CTRL_boardobjgrp_e255 { + struct ctrl_boardobjgrp_mask_e255 obj_mask; +}; + +struct ctrl_boardobjgrp { + u32 obj_mask; +}; + +#endif + diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h new file mode 100644 index 00000000..76054d27 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h @@ -0,0 +1,153 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _ctrlclk_h_ +#define _ctrlclk_h_ + +#include "ctrlboardobj.h" +#include "ctrlclkavfs.h" +#include "ctrlvolt.h" + +#define CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS 4 + +/* valid clock domain values */ +#define CTRL_CLK_DOMAIN_MCLK (0x00000010) +#define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) +#define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) +#define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) +#define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000) +#define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000) +#define CTRL_CLK_DOMAIN_PWRCLK (0x00800000) +#define CTRL_CLK_DOMAIN_NVDCLK (0x01000000) +#define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000) + +#define CTRL_CLK_DOMAIN_GPCCLK (0x10000000) +#define CTRL_CLK_DOMAIN_XBARCLK (0x20000000) +#define CTRL_CLK_DOMAIN_SYSCLK (0x40000000) +#define CTRL_CLK_DOMAIN_HUBCLK (0x80000000) + +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG 0x03 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER 0x04 +#define CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE 0x05 + +#define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF +#define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF + +#define CTRL_CLK_CLK_PROG_TYPE_1X 0x00 +#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01 +#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02 +#define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03 +#define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 + +/*! + * Enumeration of CLK_PROG source types. + */ +#define CTRL_CLK_PROG_1X_SOURCE_PLL 0x00 +#define CTRL_CLK_PROG_1X_SOURCE_ONE_SOURCE 0x01 +#define CTRL_CLK_PROG_1X_SOURCE_FLL 0x02 +#define CTRL_CLK_PROG_1X_SOURCE_INVALID 255 + +#define CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES 4 +#define CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES 6 + +#define CTRL_CLK_CLK_VF_POINT_IDX_INVALID 255 + +#define CTRL_CLK_CLK_VF_POINT_TYPE_FREQ 0x00 +#define CTRL_CLK_CLK_VF_POINT_TYPE_VOLT 0x01 +#define CTRL_CLK_CLK_VF_POINT_TYPE_UNKNOWN 255 + +struct ctrl_clk_clk_prog_1x_master_source_fll { + u32 base_vfsmooth_volt_uv; + u32 max_vf_ramprate; + u32 max_freq_stepsize_mhz; +}; + +union ctrl_clk_clk_prog_1x_master_source_data { + struct ctrl_clk_clk_prog_1x_master_source_fll fll; +}; + +struct ctrl_clk_clk_vf_point_info_freq { + u16 freq_mhz; +}; + +struct ctrl_clk_clk_vf_point_info_volt { + u32 sourceVoltageuV; + u8 vfGainVfeEquIdx; + u8 clkDomainIdx; +}; + +struct ctrl_clk_clk_prog_1x_master_vf_entry { + u8 vfe_idx; + u8 gain_vfe_idx; + u8 vf_point_idx_first; + u8 vf_point_idx_last; +}; + +struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry { + u8 clk_dom_idx; + u8 ratio; +}; + +struct ctrl_clk_clk_prog_1x_master_table_slave_entry { + u8 clk_dom_idx; + u16 freq_mhz; +}; + +struct ctrl_clk_clk_prog_1x_source_pll { + u8 pll_idx; + u8 freq_step_size_mhz; +}; + +struct ctrl_clk_clk_delta { + int freq_delta_khz; + int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; + +}; + +union ctrl_clk_clk_prog_1x_source_data { + struct ctrl_clk_clk_prog_1x_source_pll pll; +}; + +struct ctrl_clk_vf_pair { + u16 freq_mhz; + u32 voltage_uv; +}; + +struct ctrl_clk_clk_domain_list_item { + u32 clk_domain; + u32 clk_freq_khz; + u32 clk_flags; + u8 current_regime_id; + u8 target_regime_id; +}; + +#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \ + ((pvfpair)->freq_mhz) + +#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_GET(pvfpair) \ + ((pvfpair)->voltage_uv) + +#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ + (((pvfpair)->freq_mhz) = (_freqmhz)) + +#define CTRL_CLK_VF_PAIR_FREQ_MHZ_SET(pvfpair, _freqmhz) \ + (((pvfpair)->freq_mhz) = (_freqmhz)) + + +#define CTRL_CLK_VF_PAIR_VOLTAGE_UV_SET(pvfpair, _voltageuv) \ + (((pvfpair)->voltage_uv) = (_voltageuv)) + +#endif diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h new file mode 100644 index 00000000..7e28a5d9 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h @@ -0,0 +1,88 @@ +/* + * _NVRM_COPYRIGHT_BEGIN_ + * + * Copyright 2015-2016 by NVIDIA Corporation. All rights reserved. All + * information contained herein is proprietary and confidential to NVIDIA + * Corporation. Any use, reproduction, or disclosure without the written + * permission of NVIDIA Corporation is prohibited. + * + * _NVRM_COPYRIGHT_END_ + */ + +#ifndef _ctrlclkavfs_h_ +#define _ctrlclkavfs_h_ + +#include "ctrlboardobj.h" +/*! + * Valid global VIN ID values + */ +#define CTRL_CLK_VIN_ID_SYS 0x00000000 +#define CTRL_CLK_VIN_ID_LTC 0x00000001 +#define CTRL_CLK_VIN_ID_XBAR 0x00000002 +#define CTRL_CLK_VIN_ID_GPC0 0x00000003 +#define CTRL_CLK_VIN_ID_GPC1 0x00000004 +#define CTRL_CLK_VIN_ID_GPC2 0x00000005 +#define CTRL_CLK_VIN_ID_GPC3 0x00000006 +#define CTRL_CLK_VIN_ID_GPC4 0x00000007 +#define CTRL_CLK_VIN_ID_GPC5 0x00000008 +#define CTRL_CLK_VIN_ID_GPCS 0x00000009 +#define CTRL_CLK_VIN_ID_SRAM 0x0000000A +#define CTRL_CLK_VIN_ID_UNDEFINED 0x000000FF + +#define CTRL_CLK_VIN_TYPE_DISABLED 0x00000000 + +/*! + * Mask of all GPC VIN IDs supported by RM + */ +#define CTRL_CLK_VIN_MASK_UNICAST_GPC (BIT(CTRL_CLK_VIN_ID_GPC0) | \ + BIT(CTRL_CLK_VIN_ID_GPC1) | \ + BIT(CTRL_CLK_VIN_ID_GPC2) | \ + BIT(CTRL_CLK_VIN_ID_GPC3) | \ + BIT(CTRL_CLK_VIN_ID_GPC4) | \ + BIT(CTRL_CLK_VIN_ID_GPC5)) +#define CTRL_CLK_LUT_NUM_ENTRIES 0x50 +#define CTRL_CLK_VIN_STEP_SIZE_UV (10000) +#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) +#define CTRL_CLK_FLL_TYPE_DISABLED 0 + +#define CTRL_CLK_FLL_ID_SYS (0x00000000) +#define CTRL_CLK_FLL_ID_LTC (0x00000001) +#define CTRL_CLK_FLL_ID_XBAR (0x00000002) +#define CTRL_CLK_FLL_ID_GPC0 (0x00000003) +#define CTRL_CLK_FLL_ID_GPC1 (0x00000004) +#define CTRL_CLK_FLL_ID_GPC2 (0x00000005) +#define CTRL_CLK_FLL_ID_GPC3 (0x00000006) +#define CTRL_CLK_FLL_ID_GPC4 (0x00000007) +#define CTRL_CLK_FLL_ID_GPC5 (0x00000008) +#define CTRL_CLK_FLL_ID_GPCS (0x00000009) +#define CTRL_CLK_FLL_ID_UNDEFINED (0x000000FF) +#define CTRL_CLK_FLL_MASK_UNDEFINED (0x00000000) + +/*! + * Mask of all GPC FLL IDs supported by RM + */ +#define CTRL_CLK_FLL_MASK_UNICAST_GPC (BIT(CTRL_CLK_FLL_ID_GPC0) | \ + BIT(CTRL_CLK_FLL_ID_GPC1) | \ + BIT(CTRL_CLK_FLL_ID_GPC2) | \ + BIT(CTRL_CLK_FLL_ID_GPC3) | \ + BIT(CTRL_CLK_FLL_ID_GPC4) | \ + BIT(CTRL_CLK_FLL_ID_GPC5)) +/*! + * Mask of all FLL IDs supported by RM + */ +#define CTRL_CLK_FLL_ID_ALL_MASK (BIT(CTRL_CLK_FLL_ID_SYS) | \ + BIT(CTRL_CLK_FLL_ID_LTC) | \ + BIT(CTRL_CLK_FLL_ID_XBAR) | \ + BIT(CTRL_CLK_FLL_ID_GPC0) | \ + BIT(CTRL_CLK_FLL_ID_GPC1) | \ + BIT(CTRL_CLK_FLL_ID_GPC2) | \ + BIT(CTRL_CLK_FLL_ID_GPC3) | \ + BIT(CTRL_CLK_FLL_ID_GPC4) | \ + BIT(CTRL_CLK_FLL_ID_GPC5) | \ + BIT(CTRL_CLK_FLL_ID_GPCS)) + +#define CTRL_CLK_FLL_REGIME_ID_INVALID (0x00000000) +#define CTRL_CLK_FLL_REGIME_ID_FFR (0x00000001) +#define CTRL_CLK_FLL_REGIME_ID_FR (0x00000002) + +#endif diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h new file mode 100644 index 00000000..89697dfd --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h @@ -0,0 +1,32 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _ctrlperf_h_ +#define _ctrlperf_h_ + +#include "ctrlvolt.h" + +struct ctrl_perf_volt_rail_list_item { + u8 volt_domain; + u32 voltage_uv; + u32 voltage_min_noise_unaware_uv; +}; + +struct ctrl_perf_volt_rail_list { + u8 num_rails; + struct ctrl_perf_volt_rail_list_item + rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; +}; + +#endif diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h new file mode 100644 index 00000000..b4769a18 --- /dev/null +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h @@ -0,0 +1,40 @@ +/* + * general p state infrastructure + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _ctrlvolt_h_ +#define _ctrlvolt_h_ + +#define CTRL_VOLT_VOLT_RAIL_MAX_RAILS \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS + +#include "ctrlperf.h" +#include "ctrlboardobj.h" + +#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 +#define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8) +#define CTRL_VOLT_DOMAIN_INVALID 0x00 +#define CTRL_VOLT_DOMAIN_LOGIC 0x01 + +struct ctrl_volt_volt_rail_list_item { + u8 rail_idx; + u32 voltage_uv; +}; + +struct ctrl_volt_volt_rail_list { + u8 num_rails; + struct ctrl_volt_volt_rail_list_item + rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; +}; + +#endif -- cgit v1.2.2