From eb8db3e4df159210ca9c7f834dbbc939a5c67a96 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 7 Jun 2017 14:53:58 +0530 Subject: gpu: nvgpu: add APIs to export fuse offsets Add below new APIs in common/linux/fuse.c and export them from include/nvgpu/fuse.h to read/write specific tegra fuse offsets void nvgpu_tegra_fuse_write_bypass(u32 val); void nvgpu_tegra_fuse_write_access_sw(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); These APIs are needed to remove nvgpu's direct dependency on platform specific header Remove below generic APIs since they are no longer needed : nvgpu_tegra_fuse_read() nvgpu_tegra_fuse_write() Jira NVGPU-75 Change-Id: I366e6a3382f0c392b2132f4d3a7e286306bb2ec2 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1497517 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/common/linux/fuse.c | 36 +++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/common') diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c index 5c832a2a..993cbc5a 100644 --- a/drivers/gpu/nvgpu/common/linux/fuse.c +++ b/drivers/gpu/nvgpu/common/linux/fuse.c @@ -15,17 +15,41 @@ #include -int nvgpu_tegra_fuse_read(unsigned long offset, u32 *value) +int nvgpu_tegra_get_gpu_speedo_id(void) { - return tegra_fuse_readl(offset, value); + return tegra_sku_info.gpu_speedo_id; } -void nvgpu_tegra_fuse_write(u32 value, unsigned long offset) +/* + * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 + * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 + */ +void nvgpu_tegra_fuse_write_bypass(u32 val) { - tegra_fuse_control_write(value, offset); + tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); } -int nvgpu_tegra_get_gpu_speedo_id(void) +void nvgpu_tegra_fuse_write_access_sw(u32 val) { - return tegra_sku_info.gpu_speedo_id; + tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); +} + +void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val) +{ + tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); +} + +void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val) +{ + tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); +} + +int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val) +{ + return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); +} + +int nvgpu_tegra_fuse_read_reserved_calib(u32 *val) +{ + return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); } -- cgit v1.2.2