From e808d345f11885453fc65862ec4e3dd4a375ff6d Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 4 Jul 2017 11:25:00 +0530 Subject: gpu: nvgpu: rename gk20a_pmu_cmd_post() - rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 2 +- drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 6 +++--- drivers/gpu/nvgpu/common/pmu/pmu_pg.c | 16 ++++++++-------- 3 files changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/common') diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 5edfe4cd..dcf6db9c 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c @@ -478,7 +478,7 @@ clean_up: return err; } -int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, +int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, struct pmu_msg *msg, struct pmu_payload *payload, u32 queue_id, pmu_callback callback, void *cb_param, u32 *seq_desc, unsigned long timeout) diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 750906ce..f87bd175 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c @@ -112,7 +112,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu) payload.in.offset = pv->get_perfmon_cmd_init_offsetofvar(COUNTER_ALLOC); nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_INIT"); - gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, NULL, NULL, &seq, ~0); return 0; @@ -160,7 +160,7 @@ int nvgpu_pmu_perfmon_start_sampling(struct nvgpu_pmu *pmu) pv->get_perfmon_cmd_start_offsetofvar(COUNTER_ALLOC); nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_START"); - gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, PMU_COMMAND_QUEUE_LPQ, NULL, NULL, &seq, ~0); return 0; @@ -183,7 +183,7 @@ int nvgpu_pmu_perfmon_stop_sampling(struct nvgpu_pmu *pmu) cmd.cmd.perfmon.stop.cmd_type = PMU_PERFMON_CMD_ID_STOP; nvgpu_pmu_dbg(g, "cmd post PMU_PERFMON_CMD_ID_STOP"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, NULL, NULL, &seq, ~0); return 0; } diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 47ac8b64..06dab8ea 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c @@ -151,7 +151,7 @@ static int pmu_enable_elpg_locked(struct gk20a *g, u32 pg_engine_id) pmu->mscg_transition_state = PMU_ELPG_STAT_ON_PENDING; nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_ALLOW"); - status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, + status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, pmu, &seq, ~0); WARN_ON(status != 0); @@ -305,7 +305,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) ptr = &pmu->mscg_transition_state; nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, pmu, &seq, ~0); @@ -376,7 +376,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_INIT; nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_INIT"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, pmu, &seq, ~0); /* alloc dmem for powergating state log */ @@ -390,7 +390,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) cmd.cmd.pg.stat.data = 0; nvgpu_pmu_dbg(g, "cmd post PMU_PG_STAT_CMD_ALLOC_DMEM"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, pmu_handle_pg_stat_msg, pmu, &seq, ~0); /* disallow ELPG initially @@ -409,7 +409,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) cmd.cmd.pg.elpg_cmd.cmd = PMU_PG_ELPG_CMD_DISALLOW; nvgpu_pmu_dbg(g, "cmd post PMU_PG_ELPG_CMD_DISALLOW"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, pmu, &seq, ~0); if (g->ops.pmu.pmu_pg_set_sub_feature_mask) @@ -508,7 +508,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g) pmu->buf_loaded = false; nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, pmu_handle_pg_buf_config_msg, pmu, &desc, ~0); nvgpu_pmu_state_change(g, PMU_STATE_LOADING_PG_BUF, false); return err; @@ -544,7 +544,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g) pmu->buf_loaded = false; nvgpu_pmu_dbg(g, "cmd post PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_ZBC"); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, + nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, pmu_handle_pg_buf_config_msg, pmu, &desc, ~0); nvgpu_pmu_state_change(g, PMU_STATE_LOADING_ZBC, false); } @@ -662,7 +662,7 @@ int nvgpu_pmu_ap_send_command(struct gk20a *g, return 0x2f; } - status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, p_callback, pmu, &seq, ~0); if (status) { -- cgit v1.2.2