From 36f02cf49729b32aa241cb9f1f235749da681dd1 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 11 Aug 2017 13:35:24 -0700 Subject: gpu: nvgpu: Add struct gk20a ptr to FUSE APIs Add a pointer to struct gk20a to the FUSE APIs. This helps QNX builds avoid any static data definitions. Also this change plumbs struct gk20a in some of the Linux clk code and fixes a few minor style nits. Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1537611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta Reviewed-by: svc-mobile-coverity Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/common/linux/fuse.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/common') diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c index 993cbc5a..27851f92 100644 --- a/drivers/gpu/nvgpu/common/linux/fuse.c +++ b/drivers/gpu/nvgpu/common/linux/fuse.c @@ -15,7 +15,7 @@ #include -int nvgpu_tegra_get_gpu_speedo_id(void) +int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g) { return tegra_sku_info.gpu_speedo_id; } @@ -24,32 +24,32 @@ int nvgpu_tegra_get_gpu_speedo_id(void) * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 */ -void nvgpu_tegra_fuse_write_bypass(u32 val) +void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val) { tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); } -void nvgpu_tegra_fuse_write_access_sw(u32 val) +void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val) { tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); } -void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val) +void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val) { tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); } -void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val) +void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val) { tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); } -int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val) +int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val) { return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); } -int nvgpu_tegra_fuse_read_reserved_calib(u32 *val) +int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val) { return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); } -- cgit v1.2.2