From 2dbf961365822e38ac6b7266388fcfa503f6e52f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 Apr 2018 14:16:10 -0700 Subject: gpu: nvgpu: Move bus HAL to common Move implementation of bus HAL to common/bus. Change-Id: Ia89350f9d94f3ccfd5500a340e6a677cd7d4cfaa Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1726337 GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/bus.c | 51 --------- drivers/gpu/nvgpu/common/bus/bus.c | 51 +++++++++ drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 188 +++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/common/bus/bus_gk20a.h | 37 ++++++ drivers/gpu/nvgpu/common/bus/bus_gm20b.c | 68 +++++++++++ drivers/gpu/nvgpu/common/bus/bus_gm20b.h | 33 ++++++ 6 files changed, 377 insertions(+), 51 deletions(-) delete mode 100644 drivers/gpu/nvgpu/common/bus.c create mode 100644 drivers/gpu/nvgpu/common/bus/bus.c create mode 100644 drivers/gpu/nvgpu/common/bus/bus_gk20a.c create mode 100644 drivers/gpu/nvgpu/common/bus/bus_gk20a.h create mode 100644 drivers/gpu/nvgpu/common/bus/bus_gm20b.c create mode 100644 drivers/gpu/nvgpu/common/bus/bus_gm20b.h (limited to 'drivers/gpu/nvgpu/common') diff --git a/drivers/gpu/nvgpu/common/bus.c b/drivers/gpu/nvgpu/common/bus.c deleted file mode 100644 index 3889512a..00000000 --- a/drivers/gpu/nvgpu/common/bus.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include - -#include "gk20a/gk20a.h" - -int nvgpu_get_timestamps_zipper(struct gk20a *g, - u32 source_id, u32 count, - struct nvgpu_cpu_time_correlation_sample *samples) -{ - int err = 0; - unsigned int i = 0; - - if (gk20a_busy(g)) { - nvgpu_err(g, "GPU not powered on\n"); - err = -EINVAL; - goto end; - } - - for (i = 0; i < count; i++) { - err = g->ops.bus.read_ptimer(g, &samples[i].gpu_timestamp); - if (err) - return err; - - samples[i].cpu_timestamp = nvgpu_hr_timestamp(); - } - -end: - gk20a_idle(g); - return err; -} diff --git a/drivers/gpu/nvgpu/common/bus/bus.c b/drivers/gpu/nvgpu/common/bus/bus.c new file mode 100644 index 00000000..3889512a --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "gk20a/gk20a.h" + +int nvgpu_get_timestamps_zipper(struct gk20a *g, + u32 source_id, u32 count, + struct nvgpu_cpu_time_correlation_sample *samples) +{ + int err = 0; + unsigned int i = 0; + + if (gk20a_busy(g)) { + nvgpu_err(g, "GPU not powered on\n"); + err = -EINVAL; + goto end; + } + + for (i = 0; i < count; i++) { + err = g->ops.bus.read_ptimer(g, &samples[i].gpu_timestamp); + if (err) + return err; + + samples[i].cpu_timestamp = nvgpu_hr_timestamp(); + } + +end: + gk20a_idle(g); + return err; +} diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c new file mode 100644 index 00000000..010f8a7f --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "bus_gk20a.h" + +#include +#include +#include +#include +#include +#include +#include + +void gk20a_bus_init_hw(struct gk20a *g) +{ + u32 timeout_period, intr_en_mask = 0; + + if (nvgpu_platform_is_silicon(g)) + timeout_period = g->default_pri_timeout ? + g->default_pri_timeout : 0x186A0; + else + timeout_period = 0x186A0; + + if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) { + intr_en_mask = bus_intr_en_0_pri_squash_m() | + bus_intr_en_0_pri_fecserr_m() | + bus_intr_en_0_pri_timeout_m(); + gk20a_writel(g, + timer_pri_timeout_r(), + timer_pri_timeout_period_f(timeout_period) | + timer_pri_timeout_en_en_enabled_f()); + + } else { + gk20a_writel(g, + timer_pri_timeout_r(), + timer_pri_timeout_period_f(timeout_period) | + timer_pri_timeout_en_en_disabled_f()); + } + gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask); +} + +void gk20a_bus_isr(struct gk20a *g) +{ + u32 val, save0, save1, fecs_errcode = 0; + + val = gk20a_readl(g, bus_intr_0_r()); + + if (val & (bus_intr_0_pri_squash_m() | + bus_intr_0_pri_fecserr_m() | + bus_intr_0_pri_timeout_m())) { + + nvgpu_log(g, gpu_dbg_intr, "pmc_enable : 0x%x", + gk20a_readl(g, mc_enable_r())); + + save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); + if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { + /* + * write & addr fields in timeout_save0 + * might not be reliable + */ + fecs_errcode = gk20a_readl(g, + timer_pri_timeout_fecs_errcode_r()); + } + + save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); + nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " + "%s DATA 0x%08x ", + val, + timer_pri_timeout_save_0_addr_v(save0) << 2, + timer_pri_timeout_save_0_write_v(save0) ? + "WRITE" : "READ", save1); + + gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); + gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); + + if (fecs_errcode) { + nvgpu_err(g, "FECS_ERRCODE 0x%08x", fecs_errcode); + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, + fecs_errcode); + + if ((fecs_errcode & 0xffffff00) == 0xbadf1300) + nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " + "0x%08x", + gk20a_readl(g, gr_gpc0_fs_gpc_r())); + } + + } else { + nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); + } + gk20a_writel(g, bus_intr_0_r(), val); +} + +int gk20a_read_ptimer(struct gk20a *g, u64 *value) +{ + const unsigned int max_iterations = 3; + unsigned int i = 0; + u32 gpu_timestamp_hi_prev = 0; + + if (!value) + return -EINVAL; + + /* Note. The GPU nanosecond timer consists of two 32-bit + * registers (high & low). To detect a possible low register + * wrap-around between the reads, we need to read the high + * register before and after low. The wraparound happens + * approximately once per 4 secs. */ + + /* get initial gpu_timestamp_hi value */ + gpu_timestamp_hi_prev = gk20a_readl(g, timer_time_1_r()); + + for (i = 0; i < max_iterations; ++i) { + u32 gpu_timestamp_hi = 0; + u32 gpu_timestamp_lo = 0; + + gpu_timestamp_lo = gk20a_readl(g, timer_time_0_r()); + gpu_timestamp_hi = gk20a_readl(g, timer_time_1_r()); + + if (gpu_timestamp_hi == gpu_timestamp_hi_prev) { + *value = (((u64)gpu_timestamp_hi) << 32) | + gpu_timestamp_lo; + return 0; + } + + /* wrap-around detected, retry */ + gpu_timestamp_hi_prev = gpu_timestamp_hi; + } + + /* too many iterations, bail out */ + nvgpu_err(g, "failed to read ptimer"); + return -EBUSY; +} + +int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) +{ + u64 iova = nvgpu_inst_block_addr(g, bar1_inst); + u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v()); + + nvgpu_log(g, gpu_dbg_info, "bar1 inst block ptr: 0x%08x", ptr_v); + + gk20a_writel(g, bus_bar1_block_r(), + nvgpu_aperture_mask(g, bar1_inst, + bus_bar1_block_target_sys_mem_ncoh_f(), + bus_bar1_block_target_sys_mem_coh_f(), + bus_bar1_block_target_vid_mem_f()) | + bus_bar1_block_mode_virtual_f() | + bus_bar1_block_ptr_f(ptr_v)); + + return 0; +} + +void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g) +{ + /* + * Bug 1340570: increase the clock timeout to avoid potential + * operation failure at high gpcclk rate. Default values are 0x400. + */ + nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); + nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); + nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800); +} diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h new file mode 100644 index 00000000..8c07d1fe --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef BUS_GK20A_H +#define BUS_GK20A_H + +#include + +struct gk20a; +struct gpu_ops; +struct nvgpu_mem; + +void gk20a_bus_isr(struct gk20a *g); +int gk20a_read_ptimer(struct gk20a *g, u64 *value); +void gk20a_bus_init_hw(struct gk20a *g); +int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); +void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g); + +#endif /* GK20A_H */ diff --git a/drivers/gpu/nvgpu/common/bus/bus_gm20b.c b/drivers/gpu/nvgpu/common/bus/bus_gm20b.c new file mode 100644 index 00000000..3e27053a --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gm20b.c @@ -0,0 +1,68 @@ +/* + * GM20B MMU + * + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "bus_gk20a.h" +#include "bus_gm20b.h" + +#include + +int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) +{ + struct nvgpu_timeout timeout; + int err = 0; + u64 iova = nvgpu_inst_block_addr(g, bar1_inst); + u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v()); + + nvgpu_log_info(g, "bar1 inst block ptr: 0x%08x", ptr_v); + + gk20a_writel(g, bus_bar1_block_r(), + nvgpu_aperture_mask(g, bar1_inst, + bus_bar1_block_target_sys_mem_ncoh_f(), + bus_bar1_block_target_sys_mem_coh_f(), + bus_bar1_block_target_vid_mem_f()) | + bus_bar1_block_mode_virtual_f() | + bus_bar1_block_ptr_f(ptr_v)); + nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); + do { + u32 val = gk20a_readl(g, bus_bind_status_r()); + u32 pending = bus_bind_status_bar1_pending_v(val); + u32 outstanding = bus_bind_status_bar1_outstanding_v(val); + if (!pending && !outstanding) + break; + + nvgpu_udelay(5); + } while (!nvgpu_timeout_expired(&timeout)); + + if (nvgpu_timeout_peek_expired(&timeout)) + err = -EINVAL; + + return err; +} diff --git a/drivers/gpu/nvgpu/common/bus/bus_gm20b.h b/drivers/gpu/nvgpu/common/bus/bus_gm20b.h new file mode 100644 index 00000000..961b906a --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gm20b.h @@ -0,0 +1,33 @@ +/* + * GM20B BUS + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GM20B_BUS +#define _NVGPU_GM20B_BUS + +struct gk20a; +struct nvgpu_mem; + +int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); + +#endif -- cgit v1.2.2