From 03e7ef2657b4de22eff521b3e44fc4ed5cdf4dca Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 24 Mar 2017 09:39:12 -0700 Subject: gpu: nvgpu: Move Linux kernel driver code to module.c Move Linux driver specific code to common/linux/module.c. This includes module initialization, power management, and interrupt functions. Move pci.c, pci.h and nvgpu_common.c under common/linux as they're Linux only files. JIRA NVGPU-16 Change-Id: If92b4dd78ebc0c2bbfa9fbca258e9552e4979b4b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1456162 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/driver_common.c | 306 +++++++ drivers/gpu/nvgpu/common/linux/module.c | 1052 ++++++++++++++++++++++++ drivers/gpu/nvgpu/common/linux/module.h | 22 + drivers/gpu/nvgpu/common/linux/pci.c | 511 ++++++++++++ drivers/gpu/nvgpu/common/linux/pci.h | 27 + drivers/gpu/nvgpu/common/nvgpu_common.c | 292 ------- 6 files changed, 1918 insertions(+), 292 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/linux/driver_common.c create mode 100644 drivers/gpu/nvgpu/common/linux/module.c create mode 100644 drivers/gpu/nvgpu/common/linux/module.h create mode 100644 drivers/gpu/nvgpu/common/linux/pci.c create mode 100644 drivers/gpu/nvgpu/common/linux/pci.h delete mode 100644 drivers/gpu/nvgpu/common/nvgpu_common.c (limited to 'drivers/gpu/nvgpu/common') diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c new file mode 100644 index 00000000..5c96b4e8 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/driver_common.c @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a_scale.h" +#include "gk20a/gk20a.h" +#include "module.h" + +#define EMC3D_DEFAULT_RATIO 750 + +static void nvgpu_init_vars(struct gk20a *g) +{ + struct gk20a_platform *platform = dev_get_drvdata(g->dev); + + init_waitqueue_head(&g->sw_irq_stall_last_handled_wq); + init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq); + gk20a_init_gr(g); + + init_rwsem(&g->busy_lock); + + nvgpu_spinlock_init(&g->mc_enable_lock); + + nvgpu_mutex_init(&platform->railgate_lock); + nvgpu_mutex_init(&g->dbg_sessions_lock); + nvgpu_mutex_init(&g->client_lock); + nvgpu_mutex_init(&g->poweroff_lock); + + g->regs_saved = g->regs; + g->bar1_saved = g->bar1; + + g->emc3d_ratio = EMC3D_DEFAULT_RATIO; + + /* Set DMA parameters to allow larger sgt lists */ + g->dev->dma_parms = &g->dma_parms; + dma_set_max_seg_size(g->dev, UINT_MAX); + + nvgpu_init_list_node(&g->pending_sema_waits); + nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); + + nvgpu_init_list_node(&g->profiler_objects); +} + +static void nvgpu_init_timeout(struct gk20a *g) +{ + g->gr_idle_timeout_default = CONFIG_GK20A_DEFAULT_TIMEOUT; + if (nvgpu_platform_is_silicon(g)) + g->timeouts_enabled = true; + else if (nvgpu_platform_is_fpga(g)) { + g->gr_idle_timeout_default = GK20A_TIMEOUT_FPGA; + g->timeouts_enabled = true; + } +} + +static void nvgpu_init_timeslice(struct gk20a *g) +{ + g->runlist_interleave = true; + + g->timeslice_low_priority_us = 1300; + g->timeslice_medium_priority_us = 2600; + g->timeslice_high_priority_us = 5200; + + g->min_timeslice_us = 1000; + g->max_timeslice_us = 50000; +} + +static void nvgpu_init_pm_vars(struct gk20a *g) +{ + struct gk20a_platform *platform = dev_get_drvdata(g->dev); + + /* + * Set up initial power settings. For non-slicon platforms, disable + * power features and for silicon platforms, read from platform data + */ + g->slcg_enabled = + nvgpu_platform_is_silicon(g) ? platform->enable_slcg : false; + g->blcg_enabled = + nvgpu_platform_is_silicon(g) ? platform->enable_blcg : false; + g->elcg_enabled = + nvgpu_platform_is_silicon(g) ? platform->enable_elcg : false; + g->elpg_enabled = + nvgpu_platform_is_silicon(g) ? platform->enable_elpg : false; + g->aelpg_enabled = + nvgpu_platform_is_silicon(g) ? platform->enable_aelpg : false; + g->mscg_enabled = + nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false; + + /* set default values to aelpg parameters */ + g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US; + g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US; + g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US; + g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; + g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; +} + +static void nvgpu_init_mm_vars(struct gk20a *g) +{ + struct gk20a_platform *platform = dev_get_drvdata(g->dev); + + g->mm.bypass_smmu = platform->bypass_smmu; + g->mm.disable_bigpage = platform->disable_bigpage; + g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; + + nvgpu_mutex_init(&g->mm.tlb_lock); + nvgpu_mutex_init(&g->mm.priv_lock); +} + +static int gk20a_secure_page_alloc(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + int err = 0; + + if (platform->secure_page_alloc) { + err = platform->secure_page_alloc(dev); + if (!err) + platform->secure_alloc_ready = true; + } + + return err; +} + +int nvgpu_probe(struct gk20a *g, + const char *debugfs_symlink, + const char *interface_name, + struct class *class) +{ + struct gk20a_platform *platform = dev_get_drvdata(g->dev); + int err = 0; + + nvgpu_init_vars(g); + nvgpu_init_timeout(g); + nvgpu_init_timeslice(g); + nvgpu_init_pm_vars(g); + + /* Initialize the platform interface. */ + err = platform->probe(g->dev); + if (err) { + dev_err(g->dev, "platform probe failed"); + return err; + } + + /* platform probe can defer do user init only if probe succeeds */ + err = gk20a_user_init(g->dev, interface_name, class); + if (err) + return err; + + + /* Initialise scaling */ + if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) + gk20a_scale_init(g->dev); + + err = gk20a_secure_page_alloc(g->dev); + if (err) + dev_err(g->dev, + "failed to allocate secure buffer %d\n", err); + + if (platform->late_probe) { + err = platform->late_probe(g->dev); + if (err) { + dev_err(g->dev, "late probe failed"); + return err; + } + } + + nvgpu_init_mm_vars(g); + + gk20a_create_sysfs(g->dev); + gk20a_debug_init(g->dev, debugfs_symlink); + + g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); + if (!g->dbg_regops_tmp_buf) { + dev_err(g->dev, "couldn't allocate regops tmp buf"); + return -ENOMEM; + } + g->dbg_regops_tmp_buf_ops = + SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]); + + g->remove_support = gk20a_remove_support; + + kref_init(&g->refcount); + + return 0; +} + +static const struct firmware *do_request_firmware(struct device *dev, + const char *prefix, const char *fw_name, int flags) +{ + const struct firmware *fw; + char *fw_path = NULL; + int path_len, err; + + if (prefix) { + path_len = strlen(prefix) + strlen(fw_name); + path_len += 2; /* for the path separator and zero terminator*/ + + fw_path = nvgpu_kzalloc(get_gk20a(dev), + sizeof(*fw_path) * path_len); + if (!fw_path) + return NULL; + + sprintf(fw_path, "%s/%s", prefix, fw_name); + fw_name = fw_path; + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) + err = request_firmware(&fw, fw_name, dev); +#else + if (flags & NVGPU_REQUEST_FIRMWARE_NO_WARN) + err = request_firmware_direct(&fw, fw_name, dev); + else + err = request_firmware(&fw, fw_name, dev); +#endif + + nvgpu_kfree(get_gk20a(dev), fw_path); + if (err) + return NULL; + return fw; +} + +/* This is a simple wrapper around request_firmware that takes 'fw_name' and + * applies an IP specific relative path prefix to it. The caller is + * responsible for calling release_firmware later. */ +const struct firmware *nvgpu_request_firmware(struct gk20a *g, + const char *fw_name, + int flags) +{ + struct device *dev = g->dev; + const struct firmware *fw; + + /* current->fs is NULL when calling from SYS_EXIT. + Add a check here to prevent crash in request_firmware */ + if (!current->fs || !fw_name) + return NULL; + + BUG_ON(!g->name); + fw = do_request_firmware(dev, g->name, fw_name, flags); + +#ifdef CONFIG_TEGRA_GK20A + /* TO BE REMOVED - Support loading from legacy SOC specific path. */ + if (!fw && !(flags & NVGPU_REQUEST_FIRMWARE_NO_SOC)) { + struct gk20a_platform *platform = gk20a_get_platform(dev); + fw = do_request_firmware(dev, + platform->soc_name, fw_name, flags); + } +#endif + + return fw; +} + +/** + * cyclic_delta - Returns delta of cyclic integers a and b. + * + * @a - First integer + * @b - Second integer + * + * Note: if a is ahead of b, delta is positive. + */ +static int cyclic_delta(int a, int b) +{ + return a - b; +} + +/** + * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete + * + * @g - The GPU to wait on. + * + * Waits until all interrupt handlers that have been scheduled to run have + * completed. + */ +void nvgpu_wait_for_deferred_interrupts(struct gk20a *g) +{ + int stall_irq_threshold = atomic_read(&g->hw_irq_stall_count); + int nonstall_irq_threshold = atomic_read(&g->hw_irq_nonstall_count); + + /* wait until all stalling irqs are handled */ + wait_event(g->sw_irq_stall_last_handled_wq, + cyclic_delta(stall_irq_threshold, + atomic_read(&g->sw_irq_stall_last_handled)) + <= 0); + + /* wait until all non-stalling irqs are handled */ + wait_event(g->sw_irq_nonstall_last_handled_wq, + cyclic_delta(nonstall_irq_threshold, + atomic_read(&g->sw_irq_nonstall_last_handled)) + <= 0); +} diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c new file mode 100644 index 00000000..2cbf996b --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/module.c @@ -0,0 +1,1052 @@ +/* + * GK20A Graphics + * + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "vgpu/vgpu.h" +#include "gk20a/gk20a_scale.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "pci.h" +#include "module.h" +#ifdef CONFIG_TEGRA_19x_GPU +#include "nvgpu_gpuid_t19x.h" +#endif + +#define CLASS_NAME "nvidia-gpu" +/* TODO: Change to e.g. "nvidia-gpu%s" once we have symlinks in place. */ + +#define GK20A_WAIT_FOR_IDLE_MS 2000 + +#define CREATE_TRACE_POINTS +#include + +void gk20a_busy_noresume(struct device *dev) +{ + pm_runtime_get_noresume(dev); +} + +int gk20a_busy(struct gk20a *g) +{ + int ret = 0; + struct device *dev; + + if (!g) + return -ENODEV; + + atomic_inc(&g->usage_count); + + down_read(&g->busy_lock); + + if (!gk20a_can_busy(g)) { + ret = -ENODEV; + atomic_dec(&g->usage_count); + goto fail; + } + + dev = g->dev; + + if (pm_runtime_enabled(dev)) { + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + atomic_dec(&g->usage_count); + goto fail; + } + } else { + if (!g->power_on) { + ret = gk20a_gpu_is_virtual(dev) ? + vgpu_pm_finalize_poweron(dev) + : gk20a_pm_finalize_poweron(dev); + if (ret) { + atomic_dec(&g->usage_count); + goto fail; + } + } + } + + gk20a_scale_notify_busy(dev); + +fail: + up_read(&g->busy_lock); + + return ret < 0 ? ret : 0; +} + +void gk20a_idle_nosuspend(struct device *dev) +{ + pm_runtime_put_noidle(dev); +} + +void gk20a_idle(struct gk20a *g) +{ + struct device *dev; + + atomic_dec(&g->usage_count); + down_read(&g->busy_lock); + + dev = g->dev; + + if (!(dev && gk20a_can_busy(g))) + goto fail; + + if (pm_runtime_enabled(dev)) { +#ifdef CONFIG_PM + if (atomic_read(&g->dev->power.usage_count) == 1) + gk20a_scale_notify_idle(dev); +#endif + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_sync_autosuspend(dev); + + } else { + gk20a_scale_notify_idle(dev); + } +fail: + up_read(&g->busy_lock); +} + +int gk20a_pm_finalize_poweron(struct device *dev) +{ + struct gk20a *g = get_gk20a(dev); + struct gk20a_platform *platform = gk20a_get_platform(dev); + int err, nice_value; + + gk20a_dbg_fn(""); + + if (g->power_on) + return 0; + + trace_gk20a_finalize_poweron(dev_name(dev)); + + /* Increment platform power refcount */ + if (platform->busy) { + err = platform->busy(dev); + if (err < 0) { + nvgpu_err(g, "failed to poweron platform dependency"); + return err; + } + } + + err = gk20a_restore_registers(g); + if (err) + return err; + + nice_value = task_nice(current); + set_user_nice(current, -20); + + err = gk20a_finalize_poweron(g); + set_user_nice(current, nice_value); + if (err) + goto done; + + trace_gk20a_finalize_poweron_done(dev_name(dev)); + + enable_irq(g->irq_stall); + if (g->irq_stall != g->irq_nonstall) + enable_irq(g->irq_nonstall); + g->irqs_enabled = 1; + + gk20a_scale_resume(g->dev); + + if (platform->has_cde) + gk20a_init_cde_support(g); + +done: + if (err) + g->power_on = false; + + return err; +} + +static int gk20a_pm_prepare_poweroff(struct device *dev) +{ + struct gk20a *g = get_gk20a(dev); + int ret = 0; + struct gk20a_platform *platform = gk20a_get_platform(dev); + + gk20a_dbg_fn(""); + + nvgpu_mutex_acquire(&g->poweroff_lock); + + if (!g->power_on) + goto done; + + gk20a_scale_suspend(dev); + + ret = gk20a_prepare_poweroff(g); + if (ret) + goto error; + + /* + * After this point, gk20a interrupts should not get + * serviced. + */ + disable_irq(g->irq_stall); + if (g->irq_stall != g->irq_nonstall) + disable_irq(g->irq_nonstall); + + /* + * is_fmodel needs to be in gk20a struct for deferred teardown + */ + g->is_fmodel = platform->is_fmodel; + + /* Decrement platform power refcount */ + if (platform->idle) + platform->idle(dev); + + /* Stop CPU from accessing the GPU registers. */ + gk20a_lockout_registers(g); + + nvgpu_mutex_release(&g->poweroff_lock); + return 0; + +error: + gk20a_scale_resume(dev); +done: + nvgpu_mutex_release(&g->poweroff_lock); + + return ret; +} + +static struct of_device_id tegra_gk20a_of_match[] = { +#ifdef CONFIG_TEGRA_GK20A + { .compatible = "nvidia,tegra124-gk20a", + .data = &gk20a_tegra_platform }, + { .compatible = "nvidia,tegra210-gm20b", + .data = &gm20b_tegra_platform }, +#ifdef CONFIG_ARCH_TEGRA_18x_SOC + { .compatible = "nvidia,tegra186-gp10b", + .data = &gp10b_tegra_platform }, +#endif +#ifdef CONFIG_TEGRA_19x_GPU + { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA, + .data = &t19x_gpu_tegra_platform }, +#endif +#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION + { .compatible = "nvidia,tegra124-gk20a-vgpu", + .data = &vgpu_tegra_platform }, +#endif +#else + { .compatible = "nvidia,tegra124-gk20a", + .data = &gk20a_generic_platform }, + { .compatible = "nvidia,tegra210-gm20b", + .data = &gk20a_generic_platform }, +#ifdef CONFIG_ARCH_TEGRA_18x_SOC + { .compatible = TEGRA_18x_GPU_COMPAT_TEGRA, + .data = &gk20a_generic_platform }, +#endif + +#endif + { .compatible = "nvidia,generic-gk20a", + .data = &gk20a_generic_platform }, + { .compatible = "nvidia,generic-gm20b", + .data = &gk20a_generic_platform }, +#ifdef CONFIG_ARCH_TEGRA_18x_SOC + { .compatible = "nvidia,generic-gp10b", + .data = &gk20a_generic_platform }, +#endif + { }, +}; + +#ifdef CONFIG_PM +/** + * __gk20a_do_idle() - force the GPU to idle and railgate + * + * In success, this call MUST be balanced by caller with __gk20a_do_unidle() + * + * Acquires two locks : &g->busy_lock and &platform->railgate_lock + * In success, we hold these locks and return + * In failure, we release these locks and return + */ +int __gk20a_do_idle(struct device *dev, bool force_reset) +{ + struct gk20a *g = get_gk20a(dev); + struct gk20a_platform *platform = dev_get_drvdata(dev); + struct nvgpu_timeout timeout; + int ref_cnt; + int target_ref_cnt = 0; + bool is_railgated; + int err = 0; + + /* acquire busy lock to block other busy() calls */ + down_write(&g->busy_lock); + + /* acquire railgate lock to prevent unrailgate in midst of do_idle() */ + nvgpu_mutex_acquire(&platform->railgate_lock); + + /* check if it is already railgated ? */ + if (platform->is_railgated(dev)) + return 0; + + /* + * release railgate_lock, prevent suspend by incrementing usage counter, + * re-acquire railgate_lock + */ + nvgpu_mutex_release(&platform->railgate_lock); + pm_runtime_get_sync(dev); + + /* + * One refcount taken in this API + * If User disables rail gating, we take one more + * extra refcount + */ + if (platform->user_railgate_disabled) + target_ref_cnt = 2; + else + target_ref_cnt = 1; + nvgpu_mutex_acquire(&platform->railgate_lock); + + nvgpu_timeout_init(g, &timeout, GK20A_WAIT_FOR_IDLE_MS, + NVGPU_TIMER_CPU_TIMER); + + /* check and wait until GPU is idle (with a timeout) */ + do { + nvgpu_msleep(1); + ref_cnt = atomic_read(&dev->power.usage_count); + } while (ref_cnt != target_ref_cnt && !nvgpu_timeout_expired(&timeout)); + + if (ref_cnt != target_ref_cnt) { + nvgpu_err(g, "failed to idle - refcount %d != 1", + ref_cnt); + goto fail_drop_usage_count; + } + + /* check if global force_reset flag is set */ + force_reset |= platform->force_reset_in_do_idle; + + nvgpu_timeout_init(g, &timeout, GK20A_WAIT_FOR_IDLE_MS, + NVGPU_TIMER_CPU_TIMER); + + if (platform->can_railgate && !force_reset) { + /* + * Case 1 : GPU railgate is supported + * + * if GPU is now idle, we will have only one ref count, + * drop this ref which will rail gate the GPU + */ + pm_runtime_put_sync(dev); + + /* add sufficient delay to allow GPU to rail gate */ + nvgpu_msleep(platform->railgate_delay); + + /* check in loop if GPU is railgated or not */ + do { + nvgpu_msleep(1); + is_railgated = platform->is_railgated(dev); + } while (!is_railgated && !nvgpu_timeout_expired(&timeout)); + + if (is_railgated) { + return 0; + } else { + nvgpu_err(g, "failed to idle in timeout"); + goto fail_timeout; + } + } else { + /* + * Case 2 : GPU railgate is not supported or we explicitly + * do not want to depend on runtime PM + * + * if GPU is now idle, call prepare_poweroff() to save the + * state and then do explicit railgate + * + * __gk20a_do_unidle() needs to unrailgate, call + * finalize_poweron(), and then call pm_runtime_put_sync() + * to balance the GPU usage counter + */ + + /* Save the GPU state */ + err = gk20a_pm_prepare_poweroff(dev); + if (err) + goto fail_drop_usage_count; + + /* railgate GPU */ + platform->railgate(dev); + + nvgpu_udelay(10); + + g->forced_reset = true; + return 0; + } + +fail_drop_usage_count: + pm_runtime_put_noidle(dev); +fail_timeout: + nvgpu_mutex_release(&platform->railgate_lock); + up_write(&g->busy_lock); + return -EBUSY; +} + +/** + * gk20a_do_idle() - wrap up for __gk20a_do_idle() to be called + * from outside of GPU driver + * + * In success, this call MUST be balanced by caller with gk20a_do_unidle() + */ +int gk20a_do_idle(void) +{ + struct device_node *node = + of_find_matching_node(NULL, tegra_gk20a_of_match); + struct platform_device *pdev = of_find_device_by_node(node); + + int ret = __gk20a_do_idle(&pdev->dev, true); + + of_node_put(node); + + return ret; +} + +/** + * __gk20a_do_unidle() - unblock all the tasks blocked by __gk20a_do_idle() + */ +int __gk20a_do_unidle(struct device *dev) +{ + struct gk20a *g = get_gk20a(dev); + struct gk20a_platform *platform = dev_get_drvdata(dev); + int err; + + if (g->forced_reset) { + /* + * If we did a forced-reset/railgate + * then unrailgate the GPU here first + */ + platform->unrailgate(dev); + + /* restore the GPU state */ + err = gk20a_pm_finalize_poweron(dev); + if (err) + return err; + + /* balance GPU usage counter */ + pm_runtime_put_sync(dev); + + g->forced_reset = false; + } + + /* release the lock and open up all other busy() calls */ + nvgpu_mutex_release(&platform->railgate_lock); + up_write(&g->busy_lock); + + return 0; +} + +/** + * gk20a_do_unidle() - wrap up for __gk20a_do_unidle() + */ +int gk20a_do_unidle(void) +{ + struct device_node *node = + of_find_matching_node(NULL, tegra_gk20a_of_match); + struct platform_device *pdev = of_find_device_by_node(node); + + int ret = __gk20a_do_unidle(&pdev->dev); + + of_node_put(node); + + return ret; +} +#endif + +static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, + struct resource **out) +{ + struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, i); + + if (!r) + return NULL; + if (out) + *out = r; + return devm_ioremap_resource(&dev->dev, r); +} + +static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id) +{ + struct gk20a *g = dev_id; + + return g->ops.mc.isr_stall(g); +} + +static irqreturn_t gk20a_intr_isr_nonstall(int irq, void *dev_id) +{ + struct gk20a *g = dev_id; + + return g->ops.mc.isr_nonstall(g); +} + +static irqreturn_t gk20a_intr_thread_stall(int irq, void *dev_id) +{ + struct gk20a *g = dev_id; + + return g->ops.mc.isr_thread_stall(g); +} + +void gk20a_remove_support(struct gk20a *g) +{ +#ifdef CONFIG_TEGRA_COMMON + tegra_unregister_idle_unidle(); +#endif + nvgpu_kfree(g, g->dbg_regops_tmp_buf); + + if (g->pmu.remove_support) + g->pmu.remove_support(&g->pmu); + + if (g->gr.remove_support) + g->gr.remove_support(&g->gr); + + if (g->mm.remove_ce_support) + g->mm.remove_ce_support(&g->mm); + + if (g->fifo.remove_support) + g->fifo.remove_support(&g->fifo); + + if (g->mm.remove_support) + g->mm.remove_support(&g->mm); + + if (g->sim.remove_support) + g->sim.remove_support(&g->sim); + + /* free mappings to registers, etc */ + + if (g->regs) { + iounmap(g->regs); + g->regs = NULL; + } + if (g->bar1) { + iounmap(g->bar1); + g->bar1 = NULL; + } +} + +static int gk20a_init_support(struct platform_device *dev) +{ + int err = 0; + struct gk20a *g = get_gk20a(&dev->dev); + +#ifdef CONFIG_TEGRA_COMMON + tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle); +#endif + + g->regs = gk20a_ioremap_resource(dev, GK20A_BAR0_IORESOURCE_MEM, + &g->reg_mem); + if (IS_ERR(g->regs)) { + nvgpu_err(g, "failed to remap gk20a registers"); + err = PTR_ERR(g->regs); + goto fail; + } + + g->bar1 = gk20a_ioremap_resource(dev, GK20A_BAR1_IORESOURCE_MEM, + &g->bar1_mem); + if (IS_ERR(g->bar1)) { + nvgpu_err(g, "failed to remap gk20a bar1"); + err = PTR_ERR(g->bar1); + goto fail; + } + + if (nvgpu_platform_is_simulation(g)) { + g->sim.g = g; + g->sim.regs = gk20a_ioremap_resource(dev, + GK20A_SIM_IORESOURCE_MEM, + &g->sim.reg_mem); + if (IS_ERR(g->sim.regs)) { + nvgpu_err(g, "failed to remap gk20a sim regs"); + err = PTR_ERR(g->sim.regs); + goto fail; + } + + err = gk20a_init_sim_support(dev); + if (err) + goto fail; + } + + return 0; + +fail: + return err; +} + +static int gk20a_pm_railgate(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + int ret = 0; +#ifdef CONFIG_DEBUG_FS + struct gk20a *g = get_gk20a(dev); + + g->pstats.last_rail_gate_start = jiffies; + + if (g->pstats.railgating_cycle_count >= 1) + g->pstats.total_rail_ungate_time_ms = + g->pstats.total_rail_ungate_time_ms + + jiffies_to_msecs(g->pstats.last_rail_gate_start - + g->pstats.last_rail_ungate_complete); +#endif + + if (platform->railgate) + ret = platform->railgate(dev); + +#ifdef CONFIG_DEBUG_FS + g->pstats.last_rail_gate_complete = jiffies; +#endif + + return ret; +} + +static int gk20a_pm_unrailgate(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + int ret = 0; + struct gk20a *g = get_gk20a(dev); + +#ifdef CONFIG_DEBUG_FS + g->pstats.last_rail_ungate_start = jiffies; + if (g->pstats.railgating_cycle_count >= 1) + g->pstats.total_rail_gate_time_ms = + g->pstats.total_rail_gate_time_ms + + jiffies_to_msecs(g->pstats.last_rail_ungate_start - + g->pstats.last_rail_gate_complete); + + g->pstats.railgating_cycle_count++; +#endif + + trace_gk20a_pm_unrailgate(dev_name(dev)); + + if (platform->unrailgate) { + nvgpu_mutex_acquire(&platform->railgate_lock); + ret = platform->unrailgate(dev); + nvgpu_mutex_release(&platform->railgate_lock); + } + +#ifdef CONFIG_DEBUG_FS + g->pstats.last_rail_ungate_complete = jiffies; +#endif + + return ret; +} + +static void gk20a_pm_shutdown(struct platform_device *pdev) +{ + struct gk20a_platform *platform = platform_get_drvdata(pdev); + struct gk20a *g = platform->g; + int err; + + nvgpu_info(g, "shutting down"); + + /* vgpu has nothing to clean up currently */ + if (gk20a_gpu_is_virtual(&pdev->dev)) + return; + + gk20a_driver_start_unload(g); + + /* If GPU is already railgated, + * just prevent more requests, and return */ + if (platform->is_railgated && platform->is_railgated(&pdev->dev)) { + __pm_runtime_disable(&pdev->dev, false); + nvgpu_info(g, "already railgated, shut down complete"); + return; + } + + /* Prevent more requests by disabling Runtime PM */ + __pm_runtime_disable(&pdev->dev, false); + + err = gk20a_wait_for_idle(&pdev->dev); + if (err) { + nvgpu_err(g, "failed to idle GPU, err=%d", err); + goto finish; + } + + err = gk20a_fifo_disable_all_engine_activity(g, true); + if (err) { + nvgpu_err(g, "failed to disable engine activity, err=%d", + err); + goto finish; + } + + err = gk20a_fifo_wait_engine_idle(g); + if (err) { + nvgpu_err(g, "failed to idle engines, err=%d", + err); + goto finish; + } + + if (gk20a_gpu_is_virtual(&pdev->dev)) + err = vgpu_pm_prepare_poweroff(&pdev->dev); + else + err = gk20a_pm_prepare_poweroff(&pdev->dev); + if (err) { + nvgpu_err(g, "failed to prepare for poweroff, err=%d", + err); + goto finish; + } + + err = gk20a_pm_railgate(&pdev->dev); + if (err) + nvgpu_err(g, "failed to railgate, err=%d", err); + +finish: + nvgpu_info(g, "shut down complete"); +} + +#ifdef CONFIG_PM +static int gk20a_pm_runtime_resume(struct device *dev) +{ + int err = 0; + + err = gk20a_pm_unrailgate(dev); + if (err) + goto fail; + + err = gk20a_pm_finalize_poweron(dev); + if (err) + goto fail_poweron; + + return 0; + +fail_poweron: + gk20a_pm_railgate(dev); +fail: + return err; +} + +static int gk20a_pm_runtime_suspend(struct device *dev) +{ + int err = 0; + + err = gk20a_pm_prepare_poweroff(dev); + if (err) + goto fail; + + err = gk20a_pm_railgate(dev); + if (err) + goto fail_railgate; + + return 0; + +fail_railgate: + gk20a_pm_finalize_poweron(dev); +fail: + pm_runtime_mark_last_busy(dev); + return err; +} + +static int gk20a_pm_suspend(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + struct gk20a *g = get_gk20a(dev); + int ret = 0; + + if (platform->user_railgate_disabled) + gk20a_idle_nosuspend(dev); + + if (atomic_read(&dev->power.usage_count) > 1) { + ret = -EBUSY; + goto fail; + } + + if (!g->power_on) + return 0; + + ret = gk20a_pm_runtime_suspend(dev); + if (ret) + goto fail; + + if (platform->suspend) + platform->suspend(dev); + + g->suspended = true; + + return 0; + +fail: + if (platform->user_railgate_disabled) + gk20a_busy_noresume(dev); + + return ret; +} + +static int gk20a_pm_resume(struct device *dev) +{ + struct gk20a *g = get_gk20a(dev); + struct gk20a_platform *platform = dev_get_drvdata(dev); + int ret = 0; + + if (platform->user_railgate_disabled) + gk20a_busy_noresume(dev); + + if (!g->suspended) + return 0; + + ret = gk20a_pm_runtime_resume(dev); + + g->suspended = false; + + return ret; +} + +static const struct dev_pm_ops gk20a_pm_ops = { + .runtime_resume = gk20a_pm_runtime_resume, + .runtime_suspend = gk20a_pm_runtime_suspend, + .resume = gk20a_pm_resume, + .suspend = gk20a_pm_suspend, +}; +#endif + +int gk20a_pm_init(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + int err = 0; + + gk20a_dbg_fn(""); + + /* Initialise pm runtime */ + if (platform->railgate_delay) { + pm_runtime_set_autosuspend_delay(dev, + platform->railgate_delay); + pm_runtime_use_autosuspend(dev); + } + + if (platform->can_railgate) { + pm_runtime_enable(dev); + if (!pm_runtime_enabled(dev)) + gk20a_pm_unrailgate(dev); + else + gk20a_pm_railgate(dev); + } else { + __pm_runtime_disable(dev, false); + gk20a_pm_unrailgate(dev); + } + + return err; +} + +static inline void set_gk20a(struct platform_device *pdev, struct gk20a *gk20a) +{ + gk20a_get_platform(&pdev->dev)->g = gk20a; +} + +static int gk20a_probe(struct platform_device *dev) +{ + struct gk20a *gk20a; + int err; + struct gk20a_platform *platform = NULL; + + if (dev->dev.of_node) { + const struct of_device_id *match; + + match = of_match_device(tegra_gk20a_of_match, &dev->dev); + if (match) + platform = (struct gk20a_platform *)match->data; + } else + platform = (struct gk20a_platform *)dev->dev.platform_data; + + if (!platform) { + dev_err(&dev->dev, "no platform data\n"); + return -ENODATA; + } + + gk20a_dbg_fn(""); + + platform_set_drvdata(dev, platform); + + if (gk20a_gpu_is_virtual(&dev->dev)) + return vgpu_probe(dev); + + gk20a = kzalloc(sizeof(struct gk20a), GFP_KERNEL); + if (!gk20a) { + dev_err(&dev->dev, "couldn't allocate gk20a support"); + return -ENOMEM; + } + + set_gk20a(dev, gk20a); + gk20a->dev = &dev->dev; + + if (nvgpu_platform_is_simulation(gk20a)) + platform->is_fmodel = true; + + nvgpu_kmem_init(gk20a); + + gk20a->irq_stall = platform_get_irq(dev, 0); + gk20a->irq_nonstall = platform_get_irq(dev, 1); + if (gk20a->irq_stall < 0 || gk20a->irq_nonstall < 0) + return -ENXIO; + + err = devm_request_threaded_irq(&dev->dev, + gk20a->irq_stall, + gk20a_intr_isr_stall, + gk20a_intr_thread_stall, + 0, "gk20a_stall", gk20a); + if (err) { + dev_err(&dev->dev, + "failed to request stall intr irq @ %d\n", + gk20a->irq_stall); + return err; + } + err = devm_request_irq(&dev->dev, + gk20a->irq_nonstall, + gk20a_intr_isr_nonstall, + 0, "gk20a_nonstall", gk20a); + if (err) { + dev_err(&dev->dev, + "failed to request non-stall intr irq @ %d\n", + gk20a->irq_nonstall); + return err; + } + disable_irq(gk20a->irq_stall); + if (gk20a->irq_stall != gk20a->irq_nonstall) + disable_irq(gk20a->irq_nonstall); + + err = gk20a_init_support(dev); + if (err) + return err; + +#ifdef CONFIG_RESET_CONTROLLER + platform->reset_control = devm_reset_control_get(&dev->dev, NULL); + if (IS_ERR(platform->reset_control)) + platform->reset_control = NULL; +#endif + + err = nvgpu_probe(gk20a, "gpu.0", INTERFACE_NAME, &nvgpu_class); + if (err) + return err; + + err = gk20a_pm_init(&dev->dev); + if (err) { + dev_err(&dev->dev, "pm init failed"); + return err; + } + + gk20a->mm.has_physical_mode = !nvgpu_is_hypervisor_mode(gk20a); + + return 0; +} + +static int __exit gk20a_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct gk20a *g = get_gk20a(dev); + struct gk20a_platform *platform = gk20a_get_platform(dev); + + gk20a_dbg_fn(""); + + if (gk20a_gpu_is_virtual(dev)) + return vgpu_remove(pdev); + + if (platform->has_cde) + gk20a_cde_destroy(g); + + gk20a_ctxsw_trace_cleanup(g); + + gk20a_sched_ctrl_cleanup(g); + + if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) + gk20a_scale_exit(dev); + + if (g->remove_support) + g->remove_support(g); + + gk20a_ce_destroy(g); + +#ifdef CONFIG_ARCH_TEGRA_18x_SOC + nvgpu_clk_arb_cleanup_arbiter(g); +#endif + + gk20a_user_deinit(dev, &nvgpu_class); + + debugfs_remove_recursive(platform->debugfs); + debugfs_remove_recursive(platform->debugfs_alias); + + gk20a_remove_sysfs(dev); + + if (platform->secure_buffer.destroy) + platform->secure_buffer.destroy(dev, + &platform->secure_buffer); + + if (pm_runtime_enabled(dev)) + pm_runtime_disable(dev); + + if (platform->remove) + platform->remove(dev); + + set_gk20a(pdev, NULL); + gk20a_put(g); + + gk20a_dbg_fn("removed"); + + return 0; +} + +static struct platform_driver gk20a_driver = { + .probe = gk20a_probe, + .remove = __exit_p(gk20a_remove), + .shutdown = gk20a_pm_shutdown, + .driver = { + .owner = THIS_MODULE, + .name = "gk20a", +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,18,0) + .probe_type = PROBE_PREFER_ASYNCHRONOUS, +#endif +#ifdef CONFIG_OF + .of_match_table = tegra_gk20a_of_match, +#endif +#ifdef CONFIG_PM + .pm = &gk20a_pm_ops, +#endif + .suppress_bind_attrs = true, + } +}; + +struct class nvgpu_class = { + .owner = THIS_MODULE, + .name = CLASS_NAME, +}; + +static int __init gk20a_init(void) +{ + + int ret; + + ret = class_register(&nvgpu_class); + if (ret) + return ret; + + ret = nvgpu_pci_init(); + if (ret) + return ret; + + return platform_driver_register(&gk20a_driver); +} + +static void __exit gk20a_exit(void) +{ + nvgpu_pci_exit(); + platform_driver_unregister(&gk20a_driver); + class_unregister(&nvgpu_class); +} + +MODULE_LICENSE("GPL v2"); +module_init(gk20a_init); +module_exit(gk20a_exit); diff --git a/drivers/gpu/nvgpu/common/linux/module.h b/drivers/gpu/nvgpu/common/linux/module.h new file mode 100644 index 00000000..45fa2f5c --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/module.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __NVGPU_COMMON_LINUX_MODULE_H__ +#define __NVGPU_COMMON_LINUX_MODULE_H__ + +struct gk20a; +struct device; + +int gk20a_pm_finalize_poweron(struct device *dev); +void gk20a_remove_support(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c new file mode 100644 index 00000000..f90b3a6e --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/pci.c @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/platform_gk20a.h" +#include "clk/clk.h" +#include "module.h" + +#include "pci.h" + +#define PCI_INTERFACE_NAME "card-%s%%s" + +static int nvgpu_pci_tegra_probe(struct device *dev) +{ + return 0; +} + +static int nvgpu_pci_tegra_remove(struct device *dev) +{ + return 0; +} + +static bool nvgpu_pci_tegra_is_railgated(struct device *pdev) +{ + return false; +} + +static long nvgpu_pci_clk_round_rate(struct device *dev, unsigned long rate) +{ + long ret = (long)rate; + + if (rate == UINT_MAX) + ret = BOOT_GPC2CLK_MHZ * 1000000UL; + + return ret; +} + +static struct gk20a_platform nvgpu_pci_device[] = { + { /* DEVICE=0x1c35 */ + /* ptimer src frequency in hz */ + .ptimer_src_freq = 31250000, + + .probe = nvgpu_pci_tegra_probe, + .remove = nvgpu_pci_tegra_remove, + + /* power management configuration */ + .railgate_delay = 500, + .can_railgate = false, + .can_elpg = true, + .enable_elpg = true, + .enable_elcg = false, + .enable_slcg = true, + .enable_blcg = true, + .enable_mscg = true, + .default_pri_timeout = 0x3ff, + + .disable_aspm = true, + + /* power management callbacks */ + .is_railgated = nvgpu_pci_tegra_is_railgated, + .clk_round_rate = nvgpu_pci_clk_round_rate, + + .default_big_page_size = SZ_64K, + + .ch_wdt_timeout_ms = 7000, + + .vidmem_is_vidmem = true, + .vbios_min_version = 0x86063000, + .hardcode_sw_threshold = true, + .ina3221_dcb_index = 0, + .ina3221_i2c_address = 0x84, + }, + { /* DEVICE=0x1c36 */ + /* ptimer src frequency in hz */ + .ptimer_src_freq = 31250000, + + .probe = nvgpu_pci_tegra_probe, + .remove = nvgpu_pci_tegra_remove, + + /* power management configuration */ + .railgate_delay = 500, + .can_railgate = false, + .can_elpg = true, + .enable_elpg = true, + .enable_elcg = false, + .enable_slcg = true, + .enable_blcg = true, + .enable_mscg = true, + .default_pri_timeout = 0x3ff, + + .disable_aspm = true, + + /* power management callbacks */ + .is_railgated = nvgpu_pci_tegra_is_railgated, + .clk_round_rate = nvgpu_pci_clk_round_rate, + + .default_big_page_size = SZ_64K, + + .ch_wdt_timeout_ms = 7000, + + .vidmem_is_vidmem = true, + .vbios_min_version = 0x86062d00, + .hardcode_sw_threshold = true, + .ina3221_dcb_index = 0, + .ina3221_i2c_address = 0x84, + }, + { /* DEVICE=0x1c37 */ + /* ptimer src frequency in hz */ + .ptimer_src_freq = 31250000, + + .probe = nvgpu_pci_tegra_probe, + .remove = nvgpu_pci_tegra_remove, + + /* power management configuration */ + .railgate_delay = 500, + .can_railgate = false, + .can_elpg = true, + .enable_elpg = true, + .enable_elcg = false, + .enable_slcg = true, + .enable_blcg = true, + .enable_mscg = true, + .default_pri_timeout = 0x3ff, + + .disable_aspm = true, + + /* power management callbacks */ + .is_railgated = nvgpu_pci_tegra_is_railgated, + .clk_round_rate = nvgpu_pci_clk_round_rate, + + .default_big_page_size = SZ_64K, + + .ch_wdt_timeout_ms = 7000, + + .vidmem_is_vidmem = true, + .vbios_min_version = 0x86063000, + .hardcode_sw_threshold = true, + .ina3221_dcb_index = 0, + .ina3221_i2c_address = 0x84, + }, + { /* DEVICE=0x1c75 */ + /* ptimer src frequency in hz */ + .ptimer_src_freq = 31250000, + + .probe = nvgpu_pci_tegra_probe, + .remove = nvgpu_pci_tegra_remove, + + /* power management configuration */ + .railgate_delay = 500, + .can_railgate = false, + .can_elpg = true, + .enable_elpg = true, + .enable_elcg = false, + .enable_slcg = true, + .enable_blcg = true, + .enable_mscg = true, + .default_pri_timeout = 0x3ff, + + .disable_aspm = true, + + /* power management callbacks */ + .is_railgated = nvgpu_pci_tegra_is_railgated, + .clk_round_rate = nvgpu_pci_clk_round_rate, + + .default_big_page_size = SZ_64K, + + .ch_wdt_timeout_ms = 7000, + + .vidmem_is_vidmem = true, + .vbios_min_version = 0x86064700, + .hardcode_sw_threshold = false, + .ina3221_dcb_index = 1, + .ina3221_i2c_address = 0x80, + } +}; + +static struct pci_device_id nvgpu_pci_table[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c35), + .class = PCI_BASE_CLASS_DISPLAY << 16, + .class_mask = 0xff << 16, + .driver_data = 0, + }, + { + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c36), + .class = PCI_BASE_CLASS_DISPLAY << 16, + .class_mask = 0xff << 16, + .driver_data = 1, + }, + { + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c37), + .class = PCI_BASE_CLASS_DISPLAY << 16, + .class_mask = 0xff << 16, + .driver_data = 2, + }, + { + PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c75), + .class = PCI_BASE_CLASS_DISPLAY << 16, + .class_mask = 0xff << 16, + .driver_data = 3, + }, + {} +}; + +static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id) +{ + struct gk20a *g = dev_id; + irqreturn_t ret_stall; + irqreturn_t ret_nonstall; + + ret_stall = g->ops.mc.isr_stall(g); + ret_nonstall = g->ops.mc.isr_nonstall(g); + +#if defined(CONFIG_PCI_MSI) + /* Send MSI EOI */ + if (g->ops.xve.rearm_msi && g->msi_enabled) + g->ops.xve.rearm_msi(g); +#endif + + return (ret_stall == IRQ_NONE) ? ret_nonstall : IRQ_WAKE_THREAD; +} + +static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id) +{ + struct gk20a *g = dev_id; + + g->ops.mc.isr_thread_stall(g); + + return IRQ_HANDLED; +} + +static int nvgpu_pci_init_support(struct pci_dev *pdev) +{ + int err = 0; + struct gk20a *g = get_gk20a(&pdev->dev); + + g->regs = ioremap(pci_resource_start(pdev, 0), + pci_resource_len(pdev, 0)); + if (IS_ERR(g->regs)) { + nvgpu_err(g, "failed to remap gk20a registers"); + err = PTR_ERR(g->regs); + goto fail; + } + + g->bar1 = ioremap(pci_resource_start(pdev, 1), + pci_resource_len(pdev, 1)); + if (IS_ERR(g->bar1)) { + nvgpu_err(g, "failed to remap gk20a bar1"); + err = PTR_ERR(g->bar1); + goto fail; + } + + return 0; + + fail: + return err; +} + +static char *nvgpu_pci_devnode(struct device *dev, umode_t *mode) +{ + if (mode) + *mode = S_IRUGO | S_IWUGO; + return kasprintf(GFP_KERNEL, "nvgpu-pci/%s", dev_name(dev)); +} + +static struct class nvgpu_pci_class = { + .owner = THIS_MODULE, + .name = "nvidia-pci-gpu", + .devnode = nvgpu_pci_devnode, +}; + +#ifdef CONFIG_PM +static int nvgpu_pci_pm_runtime_resume(struct device *dev) +{ + return gk20a_pm_finalize_poweron(dev); +} + +static int nvgpu_pci_pm_runtime_suspend(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops nvgpu_pci_pm_ops = { + .runtime_resume = nvgpu_pci_pm_runtime_resume, + .runtime_suspend = nvgpu_pci_pm_runtime_suspend, + .resume = nvgpu_pci_pm_runtime_resume, + .suspend = nvgpu_pci_pm_runtime_suspend, +}; +#endif + +static int nvgpu_pci_pm_init(struct device *dev) +{ +#ifdef CONFIG_PM + struct gk20a_platform *platform = gk20a_get_platform(dev); + + if (!platform->can_railgate) { + pm_runtime_disable(dev); + } else { + if (platform->railgate_delay) + pm_runtime_set_autosuspend_delay(dev, + platform->railgate_delay); + + /* + * Runtime PM for PCI devices is disabled by default, + * so we need to enable it first + */ + pm_runtime_use_autosuspend(dev); + pm_runtime_put_noidle(dev); + pm_runtime_allow(dev); + } +#endif + return 0; +} + +static int nvgpu_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *pent) +{ + struct gk20a_platform *platform = NULL; + struct gk20a *g; + int err; + char nodefmt[64]; + + /* make sure driver_data is a sane index */ + if (pent->driver_data >= sizeof(nvgpu_pci_device) / + sizeof(nvgpu_pci_device[0])) { + return -EINVAL; + } + + platform = &nvgpu_pci_device[pent->driver_data]; + pci_set_drvdata(pdev, platform); + + g = kzalloc(sizeof(struct gk20a), GFP_KERNEL); + if (!g) { + nvgpu_err(g, "couldn't allocate gk20a support"); + return -ENOMEM; + } + + platform->g = g; + g->dev = &pdev->dev; + + nvgpu_kmem_init(g); + + err = pci_enable_device(pdev); + if (err) + return err; + pci_set_master(pdev); + + g->pci_vendor_id = pdev->vendor; + g->pci_device_id = pdev->device; + g->pci_subsystem_vendor_id = pdev->subsystem_vendor; + g->pci_subsystem_device_id = pdev->subsystem_device; + g->pci_class = (pdev->class >> 8) & 0xFFFFU; // we only want base/sub + g->pci_revision = pdev->revision; + +#if defined(CONFIG_PCI_MSI) + err = pci_enable_msi(pdev); + if (err) { + nvgpu_err(g, + "MSI could not be enabled, falling back to legacy"); + g->msi_enabled = false; + } else + g->msi_enabled = true; +#endif + + g->irq_stall = pdev->irq; + g->irq_nonstall = pdev->irq; + if (g->irq_stall < 0) + return -ENXIO; + + err = devm_request_threaded_irq(&pdev->dev, + g->irq_stall, + nvgpu_pci_isr, + nvgpu_pci_intr_thread, +#if defined(CONFIG_PCI_MSI) + g->msi_enabled ? 0 : +#endif + IRQF_SHARED, "nvgpu", g); + if (err) { + nvgpu_err(g, + "failed to request irq @ %d", g->irq_stall); + return err; + } + disable_irq(g->irq_stall); + + /* + * is_fmodel needs to be in gk20a struct for deferred teardown + */ + g->is_fmodel = platform->is_fmodel; + + err = nvgpu_pci_init_support(pdev); + if (err) + return err; + + if (strchr(dev_name(&pdev->dev), '%')) { + nvgpu_err(g, "illegal character in device name"); + return -EINVAL; + } + + snprintf(nodefmt, sizeof(nodefmt), + PCI_INTERFACE_NAME, dev_name(&pdev->dev)); + + err = nvgpu_probe(g, "gpu_pci", nodefmt, &nvgpu_pci_class); + if (err) + return err; + + err = nvgpu_pci_pm_init(&pdev->dev); + if (err) { + nvgpu_err(g, "pm init failed"); + return err; + } + + g->mm.has_physical_mode = false; + + return 0; +} + +static void nvgpu_pci_remove(struct pci_dev *pdev) +{ + struct gk20a_platform *platform = gk20a_get_platform(&pdev->dev); + struct gk20a *g = get_gk20a(&pdev->dev); + + gk20a_dbg(gpu_dbg_shutdown, "Removing nvgpu driver!\n"); + + if (g->irqs_enabled) + disable_irq(g->irq_stall); + + devm_free_irq(&pdev->dev, g->irq_stall, g); + +#if defined(CONFIG_PCI_MSI) + if (g->msi_enabled) { + pci_disable_msi(pdev); + g->msi_enabled = false; + } +#endif + gk20a_dbg(gpu_dbg_shutdown, "IRQs disabled.\n"); + + /* + * Wait for the driver to finish up all the IOCTLs it's working on + * before cleaning up the driver's data structures. + */ + gk20a_driver_start_unload(g); + gk20a_dbg(gpu_dbg_shutdown, "Driver idle.\n"); + +#ifdef CONFIG_ARCH_TEGRA_18x_SOC + nvgpu_clk_arb_cleanup_arbiter(g); +#endif + + gk20a_user_deinit(g->dev, &nvgpu_pci_class); + gk20a_dbg(gpu_dbg_shutdown, "User de-init done.\b"); + + debugfs_remove_recursive(platform->debugfs); + debugfs_remove_recursive(platform->debugfs_alias); + + gk20a_remove_sysfs(g->dev); + + if (platform->remove) + platform->remove(g->dev); + gk20a_dbg(gpu_dbg_shutdown, "Platform remove done.\b"); + + enable_irq(g->irq_stall); + + gk20a_get_platform(&pdev->dev)->g = NULL; + gk20a_put(g); +} + +static struct pci_driver nvgpu_pci_driver = { + .name = "nvgpu", + .id_table = nvgpu_pci_table, + .probe = nvgpu_pci_probe, + .remove = nvgpu_pci_remove, +#ifdef CONFIG_PM + .driver.pm = &nvgpu_pci_pm_ops, +#endif +}; + +int __init nvgpu_pci_init(void) +{ + int ret; + + ret = class_register(&nvgpu_pci_class); + if (ret) + return ret; + + return pci_register_driver(&nvgpu_pci_driver); +} + +void __exit nvgpu_pci_exit(void) +{ + pci_unregister_driver(&nvgpu_pci_driver); + class_unregister(&nvgpu_pci_class); +} diff --git a/drivers/gpu/nvgpu/common/linux/pci.h b/drivers/gpu/nvgpu/common/linux/pci.h new file mode 100644 index 00000000..cc6b77b1 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/pci.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef NVGPU_PCI_H +#define NVGPU_PCI_H + +#ifdef CONFIG_GK20A_PCI +int nvgpu_pci_init(void); +void nvgpu_pci_exit(void); +#else +static inline int nvgpu_pci_init(void) { return 0; } +static inline void nvgpu_pci_exit(void) {} +#endif + +#endif diff --git a/drivers/gpu/nvgpu/common/nvgpu_common.c b/drivers/gpu/nvgpu/common/nvgpu_common.c deleted file mode 100644 index 0c812d34..00000000 --- a/drivers/gpu/nvgpu/common/nvgpu_common.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include -#include -#include -#include - -#include "gk20a/gk20a_scale.h" -#include "gk20a/gk20a.h" -#include "gk20a/gr_gk20a.h" - -#define EMC3D_DEFAULT_RATIO 750 - -static void nvgpu_init_vars(struct gk20a *g) -{ - struct gk20a_platform *platform = dev_get_drvdata(g->dev); - - init_waitqueue_head(&g->sw_irq_stall_last_handled_wq); - init_waitqueue_head(&g->sw_irq_nonstall_last_handled_wq); - gk20a_init_gr(g); - - init_rwsem(&g->busy_lock); - - nvgpu_spinlock_init(&g->mc_enable_lock); - - nvgpu_mutex_init(&platform->railgate_lock); - nvgpu_mutex_init(&g->dbg_sessions_lock); - nvgpu_mutex_init(&g->client_lock); - nvgpu_mutex_init(&g->poweroff_lock); - - g->regs_saved = g->regs; - g->bar1_saved = g->bar1; - - g->emc3d_ratio = EMC3D_DEFAULT_RATIO; - - /* Set DMA parameters to allow larger sgt lists */ - g->dev->dma_parms = &g->dma_parms; - dma_set_max_seg_size(g->dev, UINT_MAX); - - nvgpu_init_list_node(&g->pending_sema_waits); - nvgpu_raw_spinlock_init(&g->pending_sema_waits_lock); - - nvgpu_init_list_node(&g->profiler_objects); -} - -static void nvgpu_init_timeout(struct gk20a *g) -{ - g->gr_idle_timeout_default = CONFIG_GK20A_DEFAULT_TIMEOUT; - if (nvgpu_platform_is_silicon(g)) - g->timeouts_enabled = true; - else if (nvgpu_platform_is_fpga(g)) { - g->gr_idle_timeout_default = GK20A_TIMEOUT_FPGA; - g->timeouts_enabled = true; - } -} - -static void nvgpu_init_timeslice(struct gk20a *g) -{ - g->runlist_interleave = true; - - g->timeslice_low_priority_us = 1300; - g->timeslice_medium_priority_us = 2600; - g->timeslice_high_priority_us = 5200; - - g->min_timeslice_us = 1000; - g->max_timeslice_us = 50000; -} - -static void nvgpu_init_pm_vars(struct gk20a *g) -{ - struct gk20a_platform *platform = dev_get_drvdata(g->dev); - - /* - * Set up initial power settings. For non-slicon platforms, disable - * power features and for silicon platforms, read from platform data - */ - g->slcg_enabled = - nvgpu_platform_is_silicon(g) ? platform->enable_slcg : false; - g->blcg_enabled = - nvgpu_platform_is_silicon(g) ? platform->enable_blcg : false; - g->elcg_enabled = - nvgpu_platform_is_silicon(g) ? platform->enable_elcg : false; - g->elpg_enabled = - nvgpu_platform_is_silicon(g) ? platform->enable_elpg : false; - g->aelpg_enabled = - nvgpu_platform_is_silicon(g) ? platform->enable_aelpg : false; - g->mscg_enabled = - nvgpu_platform_is_silicon(g) ? platform->enable_mscg : false; - - /* set default values to aelpg parameters */ - g->pmu.aelpg_param[0] = APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US; - g->pmu.aelpg_param[1] = APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US; - g->pmu.aelpg_param[2] = APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US; - g->pmu.aelpg_param[3] = APCTRL_POWER_BREAKEVEN_DEFAULT_US; - g->pmu.aelpg_param[4] = APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT; -} - -static void nvgpu_init_mm_vars(struct gk20a *g) -{ - struct gk20a_platform *platform = dev_get_drvdata(g->dev); - - g->mm.bypass_smmu = platform->bypass_smmu; - g->mm.disable_bigpage = platform->disable_bigpage; - g->mm.vidmem_is_vidmem = platform->vidmem_is_vidmem; - - nvgpu_mutex_init(&g->mm.tlb_lock); - nvgpu_mutex_init(&g->mm.priv_lock); -} - -int nvgpu_probe(struct gk20a *g, - const char *debugfs_symlink, - const char *interface_name, - struct class *class) -{ - struct gk20a_platform *platform = dev_get_drvdata(g->dev); - int err = 0; - - nvgpu_init_vars(g); - nvgpu_init_timeout(g); - nvgpu_init_timeslice(g); - nvgpu_init_pm_vars(g); - - /* Initialize the platform interface. */ - err = platform->probe(g->dev); - if (err) { - dev_err(g->dev, "platform probe failed"); - return err; - } - - /* platform probe can defer do user init only if probe succeeds */ - err = gk20a_user_init(g->dev, interface_name, class); - if (err) - return err; - - - /* Initialise scaling */ - if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) - gk20a_scale_init(g->dev); - - err = gk20a_secure_page_alloc(g->dev); - if (err) - dev_err(g->dev, - "failed to allocate secure buffer %d\n", err); - - if (platform->late_probe) { - err = platform->late_probe(g->dev); - if (err) { - dev_err(g->dev, "late probe failed"); - return err; - } - } - - nvgpu_init_mm_vars(g); - - gk20a_create_sysfs(g->dev); - gk20a_debug_init(g->dev, debugfs_symlink); - - g->dbg_regops_tmp_buf = nvgpu_kzalloc(g, SZ_4K); - if (!g->dbg_regops_tmp_buf) { - dev_err(g->dev, "couldn't allocate regops tmp buf"); - return -ENOMEM; - } - g->dbg_regops_tmp_buf_ops = - SZ_4K / sizeof(g->dbg_regops_tmp_buf[0]); - - g->remove_support = gk20a_remove_support; - - kref_init(&g->refcount); - - return 0; -} - -static const struct firmware *do_request_firmware(struct device *dev, - const char *prefix, const char *fw_name, int flags) -{ - const struct firmware *fw; - char *fw_path = NULL; - int path_len, err; - - if (prefix) { - path_len = strlen(prefix) + strlen(fw_name); - path_len += 2; /* for the path separator and zero terminator*/ - - fw_path = nvgpu_kzalloc(get_gk20a(dev), - sizeof(*fw_path) * path_len); - if (!fw_path) - return NULL; - - sprintf(fw_path, "%s/%s", prefix, fw_name); - fw_name = fw_path; - } - -#if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) - err = request_firmware(&fw, fw_name, dev); -#else - if (flags & NVGPU_REQUEST_FIRMWARE_NO_WARN) - err = request_firmware_direct(&fw, fw_name, dev); - else - err = request_firmware(&fw, fw_name, dev); -#endif - - nvgpu_kfree(get_gk20a(dev), fw_path); - if (err) - return NULL; - return fw; -} - -/* This is a simple wrapper around request_firmware that takes 'fw_name' and - * applies an IP specific relative path prefix to it. The caller is - * responsible for calling release_firmware later. */ -const struct firmware *nvgpu_request_firmware(struct gk20a *g, - const char *fw_name, - int flags) -{ - struct device *dev = g->dev; - const struct firmware *fw; - - /* current->fs is NULL when calling from SYS_EXIT. - Add a check here to prevent crash in request_firmware */ - if (!current->fs || !fw_name) - return NULL; - - BUG_ON(!g->name); - fw = do_request_firmware(dev, g->name, fw_name, flags); - -#ifdef CONFIG_TEGRA_GK20A - /* TO BE REMOVED - Support loading from legacy SOC specific path. */ - if (!fw && !(flags & NVGPU_REQUEST_FIRMWARE_NO_SOC)) { - struct gk20a_platform *platform = gk20a_get_platform(dev); - fw = do_request_firmware(dev, - platform->soc_name, fw_name, flags); - } -#endif - - return fw; -} - -/** - * cyclic_delta - Returns delta of cyclic integers a and b. - * - * @a - First integer - * @b - Second integer - * - * Note: if a is ahead of b, delta is positive. - */ -static int cyclic_delta(int a, int b) -{ - return a - b; -} - -/** - * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete - * - * @g - The GPU to wait on. - * - * Waits until all interrupt handlers that have been scheduled to run have - * completed. - */ -void nvgpu_wait_for_deferred_interrupts(struct gk20a *g) -{ - int stall_irq_threshold = atomic_read(&g->hw_irq_stall_count); - int nonstall_irq_threshold = atomic_read(&g->hw_irq_nonstall_count); - - /* wait until all stalling irqs are handled */ - wait_event(g->sw_irq_stall_last_handled_wq, - cyclic_delta(stall_irq_threshold, - atomic_read(&g->sw_irq_stall_last_handled)) - <= 0); - - /* wait until all non-stalling irqs are handled */ - wait_event(g->sw_irq_nonstall_last_handled_wq, - cyclic_delta(nonstall_irq_threshold, - atomic_read(&g->sw_irq_nonstall_last_handled)) - <= 0); -} -- cgit v1.2.2