From 3a11883f7f4399ae8dffbea00c1842e3c2095937 Mon Sep 17 00:00:00 2001 From: Peng Liu Date: Tue, 30 Oct 2018 13:45:43 -0700 Subject: gpu: nvgpu: using pmu counters for load estimate PMU counters #0 and #4 are used to count total cycles and busy cycles. These counts are used by podgov to estimate GPU load. PMU idle intr status register is used to monitor overflow. Overflow rarely occurs because frequency governor reads and resets the counters at a high cadence. When overflow occurs, 100% work load is reported to frequency governor. Bug 1963732 Change-Id: I046480ebde162e6eda24577932b96cfd91b77c69 Signed-off-by: Peng Liu Reviewed-on: https://git-master.nvidia.com/r/1939547 (cherry picked from commit 34df0035194e0203f68f679acdd84e5533a48149) Reviewed-on: https://git-master.nvidia.com/r/1979495 Reviewed-by: Aaron Tian Tested-by: Aaron Tian Reviewed-by: Rajkumar Kasirajan Tested-by: Rajkumar Kasirajan Reviewed-by: Bibek Basu GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | 42 ++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) (limited to 'drivers/gpu/nvgpu/common/pmu') diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 57a4ea40..bf07bd79 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c @@ -236,6 +236,48 @@ int nvgpu_pmu_load_update(struct gk20a *g) return 0; } +int nvgpu_pmu_busy_cycles_norm(struct gk20a *g, u32 *norm) +{ + u64 busy_cycles, total_cycles; + u32 intr_status; + + gk20a_busy_noresume(g); + if (!g->power_on) { + *norm = 0; + goto exit; + } + + if (g->ops.pmu.pmu_read_idle_counter == NULL || + g->ops.pmu.pmu_reset_idle_counter == NULL || + g->ops.pmu.pmu_read_idle_intr_status == NULL || + g->ops.pmu.pmu_clear_idle_intr_status == NULL) { + *norm = PMU_BUSY_CYCLES_NORM_MAX; + goto exit; + } + + busy_cycles = g->ops.pmu.pmu_read_idle_counter(g, 4); + total_cycles = g->ops.pmu.pmu_read_idle_counter(g, 0); + intr_status = g->ops.pmu.pmu_read_idle_intr_status(g); + + g->ops.pmu.pmu_reset_idle_counter(g, 4); + g->ops.pmu.pmu_reset_idle_counter(g, 0); + + if (intr_status != 0UL) { + *norm = PMU_BUSY_CYCLES_NORM_MAX; + g->ops.pmu.pmu_clear_idle_intr_status(g); + } else if (total_cycles == 0ULL || busy_cycles > total_cycles) { + *norm = PMU_BUSY_CYCLES_NORM_MAX; + } else { + *norm = (u32)(busy_cycles * PMU_BUSY_CYCLES_NORM_MAX + / total_cycles); + } + +exit: + gk20a_idle_nosuspend(g); + + return 0; +} + void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, u32 *total_cycles) { -- cgit v1.2.2