From d28a401e6d872f7ea6abb0c5cfc8f63e0235fe21 Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Wed, 22 Aug 2018 10:42:37 +0530 Subject: gpu: nvgpu: common: fix MISRA 10.4 violations MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fix violations where an arithmetic operation is performed on signed and unsigned int types. Jira NVGPU-992 Change-Id: Iab512139a025e035ec82a9dd74245bcf1f3869fb Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1789425 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu_pg.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_pg.c') diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 4978708c..76ed0621 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c @@ -34,17 +34,17 @@ * ON => OFF is always synchronized */ /* elpg is off */ -#define PMU_ELPG_STAT_OFF 0 +#define PMU_ELPG_STAT_OFF 0U /* elpg is on */ -#define PMU_ELPG_STAT_ON 1 +#define PMU_ELPG_STAT_ON 1U /* elpg is off, ALLOW cmd has been sent, wait for ack */ -#define PMU_ELPG_STAT_ON_PENDING 2 +#define PMU_ELPG_STAT_ON_PENDING 2U /* elpg is on, DISALLOW cmd has been sent, wait for ack */ -#define PMU_ELPG_STAT_OFF_PENDING 3 +#define PMU_ELPG_STAT_OFF_PENDING 3U /* elpg is off, caller has requested on, but ALLOW * cmd hasn't been sent due to ENABLE_ALLOW delay */ -#define PMU_ELPG_STAT_OFF_ON_PENDING 4 +#define PMU_ELPG_STAT_OFF_ON_PENDING 4U #define PMU_PGENG_GR_BUFFER_IDX_INIT (0) #define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) @@ -58,7 +58,7 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, nvgpu_log_fn(g, " "); - if (status != 0) { + if (status != 0U) { nvgpu_err(g, "ELPG cmd aborted"); /* TBD: disable ELPG */ return; @@ -174,7 +174,7 @@ static int pmu_enable_elpg_locked(struct gk20a *g, u32 pg_engine_id) status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, pmu, &seq, ~0); - WARN_ON(status != 0); + WARN_ON(status != 0U); nvgpu_log_fn(g, "done"); return 0; @@ -368,7 +368,7 @@ static void pmu_handle_pg_stat_msg(struct gk20a *g, struct pmu_msg *msg, nvgpu_log_fn(g, " "); - if (status != 0) { + if (status != 0U) { nvgpu_err(g, "ELPG cmd aborted"); /* TBD: disable ELPG */ return; @@ -507,7 +507,7 @@ static void pmu_handle_pg_buf_config_msg(struct gk20a *g, struct pmu_msg *msg, nvgpu_pmu_dbg(g, "reply PMU_PG_CMD_ID_ENG_BUF_LOAD PMU_PGENG_GR_BUFFER_IDX_FECS"); - if (status != 0) { + if (status != 0U) { nvgpu_err(g, "PGENG cmd aborted"); /* TBD: disable ELPG */ return; @@ -549,7 +549,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g) g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, u64_lo32(pmu->pg_buf.gpu_va)); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, - (u8)(pmu->pg_buf.gpu_va & 0xFF)); + (u8)(pmu->pg_buf.gpu_va & 0xFFU)); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, PMU_DMAIDX_VIRT); @@ -590,7 +590,7 @@ void nvgpu_pmu_setup_hw_load_zbc(struct gk20a *g) g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base(&cmd.cmd.pg, u64_lo32(pmu->seq_buf.gpu_va)); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset(&cmd.cmd.pg, - (u8)(pmu->seq_buf.gpu_va & 0xFF)); + (u8)(pmu->seq_buf.gpu_va & 0xFFU)); g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx(&cmd.cmd.pg, PMU_DMAIDX_VIRT); -- cgit v1.2.2