From ae809fddbe90bcec0d48e1213fa36cc5ba76550d Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Tue, 28 Aug 2018 11:58:25 +0530 Subject: gpu:nvgpu: Add GV10x perf event In case of VFE update, schedule work to set P0 clocks. Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event. Fixed MISRA issues caused by this excluding external functions and MACROs Bug 2331655 Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12 Signed-off-by: Vaikundanathan S Reviewed-on: https://git-master.nvidia.com/r/1808014 Reviewed-on: https://git-master.nvidia.com/r/1813881 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_fw.c') diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index a94453fb..c2d6a921 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -1325,8 +1325,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) clk_avfs_get_vin_cal_fuse_v20; g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = nvgpu_clk_vf_change_inject_data_fill_gv10x; - g->ops.pmu_ver.clk.perf_pmu_vfe_load = - perf_pmu_vfe_load_gv10x; g->ops.pmu_ver.clk.clk_set_boot_clk = nvgpu_clk_set_boot_fll_clk_gv10x; } else { @@ -1500,8 +1498,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) clk_avfs_get_vin_cal_fuse_v10; g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = nvgpu_clk_vf_change_inject_data_fill_gp10x; - g->ops.pmu_ver.clk.perf_pmu_vfe_load = - perf_pmu_vfe_load; break; case APP_VERSION_GM20B: g->ops.pmu_ver.pg_cmd_eng_buf_load_size = -- cgit v1.2.2