From 63e6e8ee3ee9ce01b1f7d4c0014bb589df105d71 Mon Sep 17 00:00:00 2001 From: Srirangan Date: Wed, 1 Aug 2018 13:02:14 +0530 Subject: gpu: nvgpu: common: Fix MISRA 15.6 violations This fixes errors due to single statement loop bodies without braces, which is part of Rule 15.6 of MISRA. This patch covers in gpu/nvgpu/common/ JIRA NVGPU-989 Change-Id: Ic6a98a1cd04e4524dabf650e2f6e73c6b5a1db9d Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1786207 Reviewed-by: svc-misra-checker Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/common/pmu/pmu_fw.c') diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 53eae49a..fc328401 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -881,8 +881,9 @@ static void get_pmu_init_msg_pmu_queue_params_v4( queue->index = init->queue_index[tmp_id]; queue->size = init->queue_size[tmp_id]; if (tmp_id != 0) { - for (i = 0 ; i < tmp_id; i++) + for (i = 0 ; i < tmp_id; i++) { current_ptr += init->queue_size[i]; + } } queue->offset = init->queue_offset + current_ptr; } @@ -908,8 +909,9 @@ static void get_pmu_init_msg_pmu_queue_params_v5( queue->index = init->queue_index[tmp_id]; queue->size = init->queue_size[tmp_id]; if (tmp_id != 0) { - for (i = 0 ; i < tmp_id; i++) + for (i = 0 ; i < tmp_id; i++) { current_ptr += init->queue_size[i]; + } } queue->offset = init->queue_offset + current_ptr; } @@ -935,8 +937,9 @@ static void get_pmu_init_msg_pmu_queue_params_v3( queue->index = init->queue_index[tmp_id]; queue->size = init->queue_size[tmp_id]; if (tmp_id != 0) { - for (i = 0 ; i < tmp_id; i++) + for (i = 0 ; i < tmp_id; i++) { current_ptr += init->queue_size[i]; + } } queue->offset = init->queue_offset + current_ptr; } -- cgit v1.2.2