From 863b47064445b3dd5cdc354821c8d3d14deade33 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 10 Sep 2018 21:11:49 +0530 Subject: gpu: nvgpu: PMU init sequence change -Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c method nvgpu_init_pmu_support() -Modified nvgpu_init_pmu_support() to init required interface for PMU RTOS & does start PMU RTOS in secure & non-secure based on NVGPU_SEC_PRIVSECURITY flag. -Created secured_pmu_start ops under PMU ops to start PMU falcon in low secure mode. -Updated PMU ops update_lspmu_cmdline_args, setup_apertures & secured_pmu_start assignment for gp106 & gv100 to support modified PMU init sequence. -Removed duplicate PMU non-secure bootstrap code from multiple files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method to handle non secure PMU bootstrap, reused this method for need chips. JIRA NVGPU-1146 Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1818099 Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/pmu/pmu.c | 52 ++++++++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu/common/pmu/pmu.c') diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 6d1d5f00..ffc9ec39 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c @@ -290,7 +290,7 @@ skip_init: int nvgpu_init_pmu_support(struct gk20a *g) { struct nvgpu_pmu *pmu = &g->pmu; - u32 err; + int err = 0; nvgpu_log_fn(g, " "); @@ -298,24 +298,54 @@ int nvgpu_init_pmu_support(struct gk20a *g) return 0; } - err = pmu_enable_hw(pmu, true); - if (err) { - return err; - } - if (g->support_pmu) { err = nvgpu_init_pmu_setup_sw(g); - if (err) { - return err; + if (err != 0) { + goto exit; } - err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); - if (err) { - return err; + + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* + * clear halt interrupt to avoid PMU-RTOS ucode + * hitting breakpoint due to PMU halt + */ + err = nvgpu_flcn_clear_halt_intr_status(&g->pmu_flcn, + gk20a_get_gr_idle_timeout(g)); + if (err != 0) { + goto exit; + } + + if (g->ops.pmu.setup_apertures != NULL) { + g->ops.pmu.setup_apertures(g); + } + + if (g->ops.pmu.update_lspmu_cmdline_args != NULL) { + g->ops.pmu.update_lspmu_cmdline_args(g); + } + + if (g->ops.pmu.pmu_enable_irq != NULL) { + nvgpu_mutex_acquire(&g->pmu.isr_mutex); + g->ops.pmu.pmu_enable_irq(&g->pmu, true); + g->pmu.isr_enabled = true; + nvgpu_mutex_release(&g->pmu.isr_mutex); + } + + /*Once in LS mode, cpuctl_alias is only accessible*/ + if (g->ops.pmu.secured_pmu_start != NULL) { + g->ops.pmu.secured_pmu_start(g); + } + } else { + /* Do non-secure PMU boot */ + err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); + if (err != 0) { + goto exit; + } } nvgpu_pmu_state_change(g, PMU_STATE_STARTING, false); } +exit: return err; } -- cgit v1.2.2