From 2f97e683feed3c3ba3c8722c4f6ab7466bcef0c0 Mon Sep 17 00:00:00 2001 From: Sai Nikhil Date: Fri, 17 Aug 2018 10:50:17 +0530 Subject: gpu: nvgpu: common: fix MISRA Rule 10.4 MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fix violations where an arithmetic operation is performed on signed and unsigned int types. In balloc_get_order_list() the argument "int order" has been changed to a u64 because all callers of this function pass a u64 argument. JIRA NVGPU-992 Change-Id: Ie2964f9f1dfb2865a9bd6e6cdd65e7cda6c1f638 Signed-off-by: Sai Nikhil Reviewed-on: https://git-master.nvidia.com/r/1784419 Reviewed-by: svc-misra-checker Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/mm/vm_area.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/common/mm/vm_area.c') diff --git a/drivers/gpu/nvgpu/common/mm/vm_area.c b/drivers/gpu/nvgpu/common/mm/vm_area.c index 7e2b5c34..c2c0d569 100644 --- a/drivers/gpu/nvgpu/common/mm/vm_area.c +++ b/drivers/gpu/nvgpu/common/mm/vm_area.c @@ -57,7 +57,7 @@ int nvgpu_vm_area_validate_buffer(struct vm_gk20a *vm, return -EINVAL; } - if (map_addr & (vm->gmmu_page_sizes[pgsz_idx] - 1)) { + if (map_addr & (vm->gmmu_page_sizes[pgsz_idx] - 1U)) { nvgpu_err(g, "map offset must be buffer page size aligned 0x%llx", map_addr); return -EINVAL; -- cgit v1.2.2