From 3b09c9d16a778babe9fa1df273c84c106baa48c7 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Aug 2018 15:00:18 -0700 Subject: gpu: nvgpu: Move FBPA interrupt HAL to MC FBPA interrupt is reported via a register in MC. Move the HAL dealing with that interrupt to MC. JIRA NVGPU-954 Change-Id: Ic2b8439e82788f851536bcbb5cba6580f4d5ee7e Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1813520 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/mc/mc_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/common/mc') diff --git a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c index a0f26dd3..3dce9a09 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gp10b.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gp10b.c @@ -144,8 +144,8 @@ void mc_gp10b_isr_stall(struct gk20a *g) g->ops.mc.is_intr_nvlink_pending(g, mc_intr_0)) { g->ops.nvlink.isr(g); } - if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.fb.fbpa_isr) { - g->ops.fb.fbpa_isr(g); + if (mc_intr_0 & mc_intr_pfb_pending_f() && g->ops.mc.fbpa_isr) { + g->ops.mc.fbpa_isr(g); } nvgpu_log(g, gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); -- cgit v1.2.2