From e3ae03e17abd452c157545234348692364b4b9f6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 12 Sep 2018 14:51:40 -0700 Subject: gpu: nvgpu: Add MC APIs for reset masks Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/mc/mc_gv100.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'drivers/gpu/nvgpu/common/mc/mc_gv100.c') diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c index b67f9bbe..77155d14 100644 --- a/drivers/gpu/nvgpu/common/mc/mc_gv100.c +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include "mc_gp10b.h" #include "mc_gv100.h" @@ -88,3 +90,35 @@ bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; } + +u32 gv100_mc_reset_mask(struct gk20a *g, enum nvgpu_unit unit) +{ + u32 mask = 0; + + switch(unit) { + case NVGPU_UNIT_FIFO: + mask = mc_enable_pfifo_enabled_f(); + break; + case NVGPU_UNIT_PERFMON: + mask = mc_enable_perfmon_enabled_f(); + break; + case NVGPU_UNIT_GRAPH: + mask = mc_enable_pgraph_enabled_f(); + break; + case NVGPU_UNIT_BLG: + mask = mc_enable_blg_enabled_f(); + break; + case NVGPU_UNIT_PWR: + mask = mc_enable_pwr_enabled_f(); + break; + case NVGPU_UNIT_NVDEC: + mask = mc_enable_nvdec_enabled_f(); + break; + default: + nvgpu_err(g, "unknown reset unit %d", unit); + BUG(); + break; + } + + return mask; +} -- cgit v1.2.2