From 7ac0b046a538daa1a3532d3d5ae7cba1ef3295ba Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Aug 2018 14:05:16 -0700 Subject: gpu: nvgpu: Move MC HAL to common Move implementation of MC HAL to common/mc. Also bump gk20a implementation to gm20b. gk20a_mc_boot_0 was used via a HAL, but we have only one possible implementation. It also has to be anyway called directly to detect which HALs to assign, so make it a true common function. mc_gk20a_handle_intr_nonstall was also used only in os/linux/intr.c so move it there. JIRA NVGPU-954 Change-Id: I79aedc9158f90d578db0edc17b714617b52690ac Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1813519 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/mc/mc_gv100.c | 91 ++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 drivers/gpu/nvgpu/common/mc/mc_gv100.c (limited to 'drivers/gpu/nvgpu/common/mc/mc_gv100.c') diff --git a/drivers/gpu/nvgpu/common/mc/mc_gv100.c b/drivers/gpu/nvgpu/common/mc/mc_gv100.c new file mode 100644 index 00000000..28c03434 --- /dev/null +++ b/drivers/gpu/nvgpu/common/mc/mc_gv100.c @@ -0,0 +1,91 @@ +/* + * GV100 master + * + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "mc_gp10b.h" +#include "mc_gv100.h" + +#include + +void mc_gv100_intr_enable(struct gk20a *g) +{ + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffffU); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffffU); + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + mc_intr_nvlink_pending_f() | + eng_intr_mask; + + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->mc_intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); + +} + +bool gv100_mc_is_intr_nvlink_pending(struct gk20a *g, u32 mc_intr_0) +{ + return (((mc_intr_0 & mc_intr_nvlink_pending_f()) != 0U) ? true : false); +} + +bool gv100_mc_is_stall_and_eng_intr_pending(struct gk20a *g, u32 act_eng_id, + u32 *eng_intr_pending) +{ + u32 mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + u32 stall_intr, eng_intr_mask; + + eng_intr_mask = gk20a_fifo_act_eng_interrupt_mask(g, act_eng_id); + *eng_intr_pending = mc_intr_0 & eng_intr_mask; + + stall_intr = mc_intr_pfifo_pending_f() | + mc_intr_hub_pending_f() | + mc_intr_priv_ring_pending_f() | + mc_intr_pbus_pending_f() | + mc_intr_ltc_pending_f() | + mc_intr_nvlink_pending_f(); + + nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, + "mc_intr_0 = 0x%08x, eng_intr = 0x%08x", + mc_intr_0 & stall_intr, *eng_intr_pending); + + return (mc_intr_0 & (eng_intr_mask | stall_intr)) != 0U; +} -- cgit v1.2.2