From 8fe633449f92d35b60a60de647a4e8fc1b5c8936 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 Nov 2017 14:13:25 -0800 Subject: gpu: nvgpu: Add check_priv_security fuse ops -New fuse ops is added to set NVGPU_SEC_PRIVSECURITY and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags during hal initialization -For igpu non simulation platforms, fuses are read to decide if gpu should be allowed to boot or not. --Do not boot gpu if priv_sec_en is set but wpr_enabled is not set to 1 or vpr_auto_fetch_disable is not set to 0 --With priv_sec_en set, all falcons have to boot in LS mode and this needs wpr_enabled set to 1 AND vpr_auto_fetch_disable set to 0. In this case gmmu tries to pull wpr and vpr settings from tegra mc Bug 2018223 Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1595454 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c') diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index b9d3f734..0e560981 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c @@ -24,6 +24,7 @@ #include "common/linux/vgpu/fecs_trace_vgpu.h" #include "common/linux/vgpu/css_vgpu.h" #include "vgpu_gr_gm20b.h" +#include "vgpu_fuse_gm20b.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -456,6 +457,9 @@ static const struct gpu_ops vgpu_gm20b_ops = { .priv_ring = { .isr = gk20a_priv_ring_isr, }, + .fuse = { + .check_priv_security = vgpu_gm20b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, .get_litter_value = gm20b_get_litter_value, }; @@ -463,7 +467,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { int vgpu_gm20b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; gops->ltc = vgpu_gm20b_ops.ltc; gops->ce2 = vgpu_gm20b_ops.ce2; @@ -499,26 +502,19 @@ int vgpu_gm20b_init_hal(struct gk20a *g) gops->priv_ring = vgpu_gm20b_ops.priv_ring; + gops->fuse = vgpu_gm20b_ops.fuse; + /* Lone functions */ gops->chip_init_gpu_characteristics = vgpu_gm20b_ops.chip_init_gpu_characteristics; gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - } else { - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (!val) { - gk20a_dbg_info("priv security is disabled in HW"); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - } else { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - } - } + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { -- cgit v1.2.2