From 86691b59c6fae2b091855c0f4d44079cad8529b1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Dec 2017 13:04:17 -0800 Subject: gpu: nvgpu: Remove bare channel scheduling Remove scheduling IOCTL implementations for bare channels. Also removes code that constructs bare channels in runlist. Bug 1842197 Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1627326 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c | 55 ++----------------------- 1 file changed, 3 insertions(+), 52 deletions(-) (limited to 'drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c') diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c index e06b41da..6b8c630b 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c @@ -604,8 +604,8 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g) return 0; } -static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, - u32 tsgid, +int vgpu_fifo_set_runlist_interleave(struct gk20a *g, + u32 id, u32 runlist_id, u32 new_level) { @@ -618,62 +618,13 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; msg.handle = vgpu_get_handle(g); - p->tsg_id = tsgid; - p->level = new_level; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - WARN_ON(err || msg.ret); - return err ? err : msg.ret; -} - -int vgpu_fifo_set_runlist_interleave(struct gk20a *g, - u32 id, - bool is_tsg, - u32 runlist_id, - u32 new_level) -{ - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_channel_runlist_interleave_params *p = - &msg.params.channel_interleave; - struct channel_gk20a *ch; - int err; - - gk20a_dbg_fn(""); - - if (is_tsg) - return vgpu_fifo_tsg_set_runlist_interleave(g, id, - runlist_id, new_level); - - ch = &g->fifo.channel[id]; - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; - msg.handle = vgpu_get_handle(ch->g); - p->handle = ch->virt_ctx; + p->tsg_id = id; p->level = new_level; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); return err ? err : msg.ret; } -int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) -{ - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_channel_timeslice_params *p = - &msg.params.channel_timeslice; - int err; - - gk20a_dbg_fn(""); - - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE; - msg.handle = vgpu_get_handle(ch->g); - p->handle = ch->virt_ctx; - p->timeslice_us = timeslice; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - err = err ? err : msg.ret; - WARN_ON(err); - if (!err) - ch->timeslice_us = p->timeslice_us; - return err; -} - int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, u32 err_code, bool verbose) { -- cgit v1.2.2