From 25440e63d2dfd329ba35aec48f11f0c20b18cdbd Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 31 Oct 2017 06:11:57 -0700 Subject: gpu: nvgpu: move platform_gk20a.h to linux Move gk20a/platform_gk20a.h to linux specific directory as common/linux/platform_gk20a.h since this file includes all linux specific stuff Fix #includes in all the files to include this file with correct path Remove #include of this file where it is no more needed Fix gk20a_init_sim_support() to receive struct gk20a as parameter instead of receiving linux specific struct platform_device NVGPU-316 Change-Id: I5ec08e776b753af4d39d11c11f6f068be2ac236f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1589938 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/platform_gk20a.h | 302 ++++++++++++++++++++++++ 1 file changed, 302 insertions(+) create mode 100644 drivers/gpu/nvgpu/common/linux/platform_gk20a.h (limited to 'drivers/gpu/nvgpu/common/linux/platform_gk20a.h') diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h new file mode 100644 index 00000000..348c9e24 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h @@ -0,0 +1,302 @@ +/* + * GK20A Platform (SoC) Interface + * + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _GK20A_PLATFORM_H_ +#define _GK20A_PLATFORM_H_ + +#include + +#include + +#include "gk20a/gk20a.h" + +#define GK20A_CLKS_MAX 4 + +struct gk20a; +struct channel_gk20a; +struct gr_ctx_buffer_desc; +struct gk20a_scale_profile; + +struct secure_page_buffer { + void (*destroy)(struct gk20a *, struct secure_page_buffer *); + size_t size; + u64 iova; +}; + +struct gk20a_platform { + /* Populated by the gk20a driver before probing the platform. */ + struct gk20a *g; + + /* Should be populated at probe. */ + bool can_railgate_init; + + /* Should be populated at probe. */ + bool can_elpg_init; + + /* Should be populated at probe. */ + bool has_syncpoints; + + /* channel limit after which to start aggressive sync destroy */ + unsigned int aggressive_sync_destroy_thresh; + + /* flag to set sync destroy aggressiveness */ + bool aggressive_sync_destroy; + + /* set if ASPM should be disabled on boot; only makes sense for PCI */ + bool disable_aspm; + + /* Set if the platform can unify the small/large address spaces. */ + bool unify_address_spaces; + + /* Clock configuration is stored here. Platform probe is responsible + * for filling this data. */ + struct clk *clk[GK20A_CLKS_MAX]; + int num_clks; + +#ifdef CONFIG_RESET_CONTROLLER + /* Reset control for device */ + struct reset_control *reset_control; +#endif + + /* Delay before rail gated */ + int railgate_delay_init; + + /* Second Level Clock Gating: true = enable false = disable */ + bool enable_slcg; + + /* Block Level Clock Gating: true = enable flase = disable */ + bool enable_blcg; + + /* Engine Level Clock Gating: true = enable flase = disable */ + bool enable_elcg; + + /* Should be populated at probe. */ + bool can_slcg; + + /* Should be populated at probe. */ + bool can_blcg; + + /* Should be populated at probe. */ + bool can_elcg; + + /* Engine Level Power Gating: true = enable flase = disable */ + bool enable_elpg; + + /* Adaptative ELPG: true = enable flase = disable */ + bool enable_aelpg; + + /* PMU Perfmon: true = enable false = disable */ + bool enable_perfmon; + + /* Memory System Clock Gating: true = enable flase = disable*/ + bool enable_mscg; + + /* Timeout for per-channel watchdog (in mS) */ + u32 ch_wdt_timeout_ms; + + /* Enable SMMU bypass by default */ + bool bypass_smmu; + + /* Disable big page support */ + bool disable_bigpage; + + /* + * gk20a_do_idle() API can take GPU either into rail gate or CAR reset + * This flag can be used to force CAR reset case instead of rail gate + */ + bool force_reset_in_do_idle; + + /* default pri timeout, on PCIe it should be lower than timeout + * detection + */ + u32 default_pri_timeout; + + /* Initialize the platform interface of the gk20a driver. + * + * The platform implementation of this function must + * - set the power and clocks of the gk20a device to a known + * state, and + * - populate the gk20a_platform structure (a pointer to the + * structure can be obtained by calling gk20a_get_platform). + * + * After this function is finished, the driver will initialise + * pm runtime and genpd based on the platform configuration. + */ + int (*probe)(struct device *dev); + + /* Second stage initialisation - called once all power management + * initialisations are done. + */ + int (*late_probe)(struct device *dev); + + /* Remove device after power management has been done + */ + int (*remove)(struct device *dev); + + /* Poweron platform dependencies */ + int (*busy)(struct device *dev); + + /* Powerdown platform dependencies */ + void (*idle)(struct device *dev); + + struct secure_page_buffer secure_buffer; + + /* Device is going to be suspended */ + int (*suspend)(struct device *); + + /* Called to turn off the device */ + int (*railgate)(struct device *dev); + + /* Called to turn on the device */ + int (*unrailgate)(struct device *dev); + struct nvgpu_mutex railgate_lock; + + /* Called to check state of device */ + bool (*is_railgated)(struct device *dev); + + /* get supported frequency list */ + int (*get_clk_freqs)(struct device *pdev, + unsigned long **freqs, int *num_freqs); + + /* clk related supported functions */ + long (*clk_round_rate)(struct device *dev, + unsigned long rate); + + /* Called to register GPCPLL with common clk framework */ + int (*clk_register)(struct gk20a *g); + + /* Postscale callback is called after frequency change */ + void (*postscale)(struct device *dev, + unsigned long freq); + + /* Pre callback is called before frequency change */ + void (*prescale)(struct device *dev); + + /* Devfreq governor name. If scaling is enabled, we request + * this governor to be used in scaling */ + const char *devfreq_governor; + + /* Quality of service notifier callback. If this is set, the scaling + * routines will register a callback to Qos. Each time we receive + * a new value, this callback gets called. */ + int (*qos_notify)(struct notifier_block *nb, + unsigned long n, void *p); + + /* Called as part of debug dump. If the gpu gets hung, this function + * is responsible for delivering all necessary debug data of other + * hw units which may interact with the gpu without direct supervision + * of the CPU. + */ + void (*dump_platform_dependencies)(struct device *dev); + + /* Callbacks to assert/deassert GPU reset */ + int (*reset_assert)(struct device *dev); + int (*reset_deassert)(struct device *dev); + struct clk *clk_reset; + struct dvfs_rail *gpu_rail; + + bool virtual_dev; +#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION + void *vgpu_priv; +#endif + /* source frequency for ptimer in hz */ + u32 ptimer_src_freq; + + bool has_cde; + + /* soc name for finding firmware files */ + const char *soc_name; + + /* false if vidmem aperture actually points to sysmem */ + bool honors_aperture; + /* unified or split memory with separate vidmem? */ + bool unified_memory; + + /* true if all channels must be in TSG */ + bool tsg_required; + + /* minimum supported VBIOS version */ + u32 vbios_min_version; + + /* true if we run preos microcode on this board */ + bool run_preos; + + /* true if we need to program sw threshold for + * power limits + */ + bool hardcode_sw_threshold; + + /* i2c device index, port and address for INA3221 */ + u32 ina3221_dcb_index; + u32 ina3221_i2c_address; + u32 ina3221_i2c_port; +}; + +static inline struct gk20a_platform *gk20a_get_platform( + struct device *dev) +{ + return (struct gk20a_platform *)dev_get_drvdata(dev); +} + +#ifdef CONFIG_TEGRA_GK20A +extern struct gk20a_platform gm20b_tegra_platform; +extern struct gk20a_platform gp10b_tegra_platform; +#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION +extern struct gk20a_platform vgpu_tegra_platform; +#endif +#endif + +int gk20a_tegra_busy(struct device *dev); +void gk20a_tegra_idle(struct device *dev); +void gk20a_tegra_debug_dump(struct device *pdev); + +static inline struct gk20a *get_gk20a(struct device *dev) +{ + return gk20a_get_platform(dev)->g; +} +static inline struct gk20a *gk20a_from_dev(struct device *dev) +{ + if (!dev) + return NULL; + + return ((struct gk20a_platform *)dev_get_drvdata(dev))->g; +} +static inline bool gk20a_gpu_is_virtual(struct device *dev) +{ + struct gk20a_platform *platform = dev_get_drvdata(dev); + + return platform->virtual_dev; +} + +static inline int support_gk20a_pmu(struct device *dev) +{ + if (IS_ENABLED(CONFIG_GK20A_PMU)) { + /* gPMU is not supported for vgpu */ + return !gk20a_gpu_is_virtual(dev); + } + + return 0; +} + +#endif -- cgit v1.2.2