From 15ec5722be8f483f6d9c1cd0bfd61a7e2bcbfca2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 25 Apr 2018 03:08:49 -0700 Subject: gpu: nvgpu: add HAL to handle nonstall interrupts Add new HAL gops.mc.isr_nonstall() to handle nonstall interrupts We already handle nonstall interrupts in nvgpu_intr_nonstall() But this API is completely in linux specific code Separate out os-independent code to handle nonstall interrupts in new API mc_gk20a_isr_nonstall() and set it to HAL gops.mc.isr_nonstall() for all existing chips Call this HAL from nvgpu_intr_nonstall() Jira NVGPUT-8 Change-Id: Iec6a56db03158a72a256f7eee8989a0a8a42ae2f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1706589 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/intr.c | 35 ++++------------------------------- 1 file changed, 4 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/nvgpu/common/linux/intr.c') diff --git a/drivers/gpu/nvgpu/common/linux/intr.c b/drivers/gpu/nvgpu/common/linux/intr.c index 6b4b2dc9..05dd3f2a 100644 --- a/drivers/gpu/nvgpu/common/linux/intr.c +++ b/drivers/gpu/nvgpu/common/linux/intr.c @@ -69,11 +69,8 @@ irqreturn_t nvgpu_intr_thread_stall(struct gk20a *g) irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) { - u32 mc_intr_1; + u32 non_stall_intr_val; u32 hw_irq_count; - u32 engine_id_idx; - u32 active_engine_id = 0; - u32 engine_enum = ENGINE_INVAL_GK20A; int ops_old, ops_new, ops = 0; struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); @@ -81,37 +78,13 @@ irqreturn_t nvgpu_intr_nonstall(struct gk20a *g) return IRQ_NONE; /* not from gpu when sharing irq with others */ - mc_intr_1 = g->ops.mc.intr_nonstall(g); - if (unlikely(!mc_intr_1)) + non_stall_intr_val = g->ops.mc.intr_nonstall(g); + if (unlikely(!non_stall_intr_val)) return IRQ_NONE; g->ops.mc.intr_nonstall_pause(g); - if (g->ops.mc.is_intr1_pending(g, NVGPU_UNIT_FIFO, mc_intr_1)) - ops |= gk20a_fifo_nonstall_isr(g); - - for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; - engine_id_idx++) { - struct fifo_engine_info_gk20a *engine_info; - - active_engine_id = g->fifo.active_engines_list[engine_id_idx]; - engine_info = &g->fifo.engine_info[active_engine_id]; - - if (mc_intr_1 & engine_info->intr_mask) { - engine_enum = engine_info->engine_enum; - /* GR Engine */ - if (engine_enum == ENGINE_GR_GK20A) - ops |= gk20a_gr_nonstall_isr(g); - - /* CE Engine */ - if (((engine_enum == ENGINE_GRCE_GK20A) || - (engine_enum == ENGINE_ASYNC_CE_GK20A)) && - g->ops.ce2.isr_nonstall) - ops |= g->ops.ce2.isr_nonstall(g, - engine_info->inst_id, - engine_info->pri_base); - } - } + ops = g->ops.mc.isr_nonstall(g); if (ops) { do { ops_old = atomic_read(&l->nonstall_ops); -- cgit v1.2.2