From 385d3473e72c653906c82062eb2545abd7eeefe4 Mon Sep 17 00:00:00 2001 From: Srirangan Date: Thu, 23 Aug 2018 12:19:48 +0530 Subject: gpu: nvgpu: common: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I18cf871f2d1296b931d6ab43f1ac668551171dcc Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1805076 Reviewed-by: svc-misra-checker Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c') diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c index 3a26e1b9..97570f9c 100644 --- a/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gp10b.c @@ -63,16 +63,17 @@ int gp10b_fuse_check_priv_security(struct gk20a *g) GCPLEX_CONFIG_WPR_ENABLED_MASK) && !(gcplex_config & GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { - if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) + if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) { nvgpu_log(g, gpu_dbg_info, "gcplex_config = 0x%08x, " "secure mode: ACR debug", gcplex_config); - else + } else { nvgpu_log(g, gpu_dbg_info, "gcplex_config = 0x%08x, " "secure mode: ACR non debug", gcplex_config); + } } else { nvgpu_err(g, "gcplex_config = 0x%08x " -- cgit v1.2.2