From 7a26ad57a7d2fc5cec4a0c8a8395c0c666d31cba Mon Sep 17 00:00:00 2001 From: Vinod G Date: Wed, 6 Feb 2019 16:23:11 -0800 Subject: gpu: nvgpu: enable platform atomic feature Support following changes related to platform atomic feature NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW NV_PFB_FBHUB_NUM_ACTIVE_LTCS_HUB_SYS_NCOH_ATOMIC_MODE to USE_READ In gv11b, FBHUB_NUM_ACTIVE_LTCS register has read only privilege, so atomic mode register bits cannot be updated from kernel code. atomic capability and atomic_sys_ncoh_mode bits are copied from fb mmu_ctrl to gpcs_mmu_ctrl register. new tu104 hal for fb_enable_nvlink function. bug 200580236 Change-Id: Ia78986c1c56795c6efad20f4ba42700ef1c2c1ad Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/2013481 (cherry picked from commit 251e3eaa8029c4ae07b2cde7af5d9775e1cd8ec1) Signed-off-by: Lakshmanan M Reviewed-on: https://git-master.nvidia.com/r/2274932 GVS: Gerrit_Virtual_Submit Tested-by: Sreeniketh H Reviewed-by: Deepak Nibade Reviewed-by: Bibek Basu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fb/fb_gv11b.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/common/fb/fb_gv11b.c') diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c index b98d1c41..49e8f385 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B FB * - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -62,6 +62,34 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) } } +static void gv11b_fb_set_atomic_mode(struct gk20a *g) +{ + u32 reg_val; + + /* + * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE + * NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2 + */ + reg_val = nvgpu_readl(g, fb_mmu_ctrl_r()); + reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_mode_m(), + fb_mmu_ctrl_atomic_capability_mode_rmw_f()); + reg_val = set_field(reg_val, fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_m(), + fb_mmu_ctrl_atomic_capability_sys_ncoh_mode_l2_f()); + nvgpu_writel(g, fb_mmu_ctrl_r(), reg_val); + + /* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW */ + reg_val = nvgpu_readl(g, fb_hshub_num_active_ltcs_r()); + reg_val = set_field(reg_val, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(), + fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f()); + nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), reg_val); + + nvgpu_log(g, gpu_dbg_info, "fb_mmu_ctrl_r 0x%x", + gk20a_readl(g, fb_mmu_ctrl_r())); + + nvgpu_log(g, gpu_dbg_info, "fb_hshub_num_active_ltcs_r 0x%x", + gk20a_readl(g, fb_hshub_num_active_ltcs_r())); +} + void gv11b_fb_init_hw(struct gk20a *g) { gm20b_fb_init_hw(g); @@ -75,6 +103,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g) gv11b_init_nvlink_soc_credits(g); + gv11b_fb_set_atomic_mode(g); + nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x", gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); -- cgit v1.2.2