From dbb8792baf2142626728abf909fb201144b9b56a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 24 May 2018 13:00:14 -0700 Subject: gpu: nvgpu: Move setting of BAR0_WINDOW to bus Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to common code so that pramin_gk20a.[ch] can be deleted. JIRA NVGPU-588 Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730890 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers/gpu/nvgpu/common/bus/bus_gk20a.c') diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index 62dd7450..a2c6a3d7 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c @@ -169,3 +169,34 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) return 0; } + +u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, + struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w) +{ + u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl); + u64 addr = bufbase + w * sizeof(u32); + u32 hi = (u32)((addr & ~(u64)0xfffff) + >> bus_bar0_window_target_bar0_window_base_shift_v()); + u32 lo = (u32)(addr & 0xfffff); + u32 win = nvgpu_aperture_mask(g, mem, + bus_bar0_window_target_sys_mem_noncoherent_f(), + bus_bar0_window_target_sys_mem_coherent_f(), + bus_bar0_window_target_vid_mem_f()) | + bus_bar0_window_base_f(hi); + + nvgpu_log(g, gpu_dbg_mem, + "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)", + hi, lo, mem, sgl, bufbase, + bufbase + nvgpu_sgt_get_phys(g, sgt, sgl), + nvgpu_sgt_get_length(sgt, sgl)); + + WARN_ON(!bufbase); + + if (g->mm.pramin_window != win) { + gk20a_writel(g, bus_bar0_window_r(), win); + gk20a_readl(g, bus_bar0_window_r()); + g->mm.pramin_window = win; + } + + return lo; +} -- cgit v1.2.2