From 5215d65c25b5e76c19d9d12b03c52f69e2d40227 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 24 May 2018 15:25:41 -0700 Subject: gpu: nvgpu: Remove setting of PRI timeout PRI timeout should always use the HW initialization value. Do not set it explicitly. JIRA NVGPU-588 Change-Id: Idb63caba07c5fa7e0439e572861443f2783d0adc Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730892 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/nvgpu/common/bus/bus_gk20a.c') diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index d173123d..9f0446c6 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c @@ -32,29 +32,14 @@ void gk20a_bus_init_hw(struct gk20a *g) { - u32 timeout_period, intr_en_mask = 0; - - if (nvgpu_platform_is_silicon(g)) - timeout_period = g->default_pri_timeout ? - g->default_pri_timeout : 0x186A0; - else - timeout_period = 0x186A0; + u32 intr_en_mask = 0; if (nvgpu_platform_is_silicon(g) || nvgpu_platform_is_fpga(g)) { intr_en_mask = bus_intr_en_0_pri_squash_m() | bus_intr_en_0_pri_fecserr_m() | bus_intr_en_0_pri_timeout_m(); - gk20a_writel(g, - timer_pri_timeout_r(), - timer_pri_timeout_period_f(timeout_period) | - timer_pri_timeout_en_en_enabled_f()); - - } else { - gk20a_writel(g, - timer_pri_timeout_r(), - timer_pri_timeout_period_f(timeout_period) | - timer_pri_timeout_en_en_disabled_f()); } + gk20a_writel(g, bus_intr_en_0_r(), intr_en_mask); } -- cgit v1.2.2