From 1add126551309a323ae422be41c9db2203bbe112 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 6 Apr 2017 12:17:26 -0700 Subject: gpu: nvgpu: clk: Use new error macros gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I58bb9e2fb7e5b18f74fbb92b70150cce97968fc3 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1457347 Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/clk/clk.c | 21 ++++------ drivers/gpu/nvgpu/clk/clk_arb.c | 60 ++++++++++------------------- drivers/gpu/nvgpu/clk/clk_common.c | 2 +- drivers/gpu/nvgpu/clk/clk_domain.c | 14 +++---- drivers/gpu/nvgpu/clk/clk_fll.c | 12 +++--- drivers/gpu/nvgpu/clk/clk_freq_controller.c | 13 +++---- drivers/gpu/nvgpu/clk/clk_mclk.c | 21 ++++------ drivers/gpu/nvgpu/clk/clk_prog.c | 25 +++++------- drivers/gpu/nvgpu/clk/clk_vf_point.c | 18 ++++----- drivers/gpu/nvgpu/clk/clk_vin.c | 8 ++-- 10 files changed, 79 insertions(+), 115 deletions(-) (limited to 'drivers/gpu/nvgpu/clk') diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index e809b5e9..8b36394d 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c @@ -36,8 +36,7 @@ static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, gk20a_dbg_info(""); if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) { - gk20a_err(dev_from_gk20a(g), - "unsupported msg for VFE LOAD RPC %x", + nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x", msg->msg.clk.msg_type); return; } @@ -99,8 +98,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) &seqdesc, ~0); if (status) { - gk20a_err(dev_from_gk20a(g), - "unable to post clk RPC cmd %x", + nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; } @@ -110,7 +108,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) &handler.success, 1); if (handler.success == 0) { - gk20a_err(dev_from_gk20a(g), "rpc call to load freq cntlr cal failed"); + nvgpu_err(g, "rpc call to load freq cntlr cal failed"); status = -EINVAL; } @@ -159,8 +157,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) &seqdesc, ~0); if (status) { - gk20a_err(dev_from_gk20a(g), - "unable to post clk RPC cmd %x", + nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; } @@ -170,7 +167,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) &handler.success, 1); if (handler.success == 0) { - gk20a_err(dev_from_gk20a(g), "rpc call to load vin cal failed"); + nvgpu_err(g, "rpc call to load vin cal failed"); status = -EINVAL; } @@ -258,8 +255,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) &seqdesc, ~0); if (status) { - gk20a_err(dev_from_gk20a(g), - "unable to post clk RPC cmd %x", + nvgpu_err(g, "unable to post clk RPC cmd %x", cmd.cmd.clk.cmd_type); goto done; } @@ -269,7 +265,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) &handler.success, 1); if (handler.success == 0) { - gk20a_err(dev_from_gk20a(g), "rpc call to inject clock failed"); + nvgpu_err(g, "rpc call to inject clock failed"); status = -EINVAL; } done: @@ -359,8 +355,7 @@ int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *setfllclk) status = clk_pmu_vf_inject(g, setfllclk); if (status) - gk20a_err(dev_from_gk20a(g), - "vf inject to change clk failed"); + nvgpu_err(g, "vf inject to change clk failed"); /* save regime ids */ status = set_regime_id(g, CTRL_CLK_DOMAIN_XBAR2CLK, diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index b8be3334..85a5018d 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c @@ -706,14 +706,12 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) /* Get allowed memory ranges */ if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_GPC2CLK, &gpc2clk_min, &gpc2clk_max) < 0) { - gk20a_err(dev_from_gk20a(g), - "failed to fetch GPC2CLK range"); + nvgpu_err(g, "failed to fetch GPC2CLK range"); goto exit_vf_table; } if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_MCLK, &mclk_min, &mclk_max) < 0) { - gk20a_err(dev_from_gk20a(g), - "failed to fetch MCLK range"); + nvgpu_err(g, "failed to fetch MCLK range"); goto exit_vf_table; } @@ -722,20 +720,17 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_GPC2CLK, &table->gpc2clk_num_points, arb->gpc2clk_f_points)) { - gk20a_err(dev_from_gk20a(g), - "failed to fetch GPC2CLK frequency points"); + nvgpu_err(g, "failed to fetch GPC2CLK frequency points"); goto exit_vf_table; } if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_MCLK, &table->mclk_num_points, arb->mclk_f_points)) { - gk20a_err(dev_from_gk20a(g), - "failed to fetch MCLK frequency points"); + nvgpu_err(g, "failed to fetch MCLK frequency points"); goto exit_vf_table; } if (!table->mclk_num_points || !table->gpc2clk_num_points) { - gk20a_err(dev_from_gk20a(g), - "empty queries to f points mclk %d gpc2clk %d", + nvgpu_err(g, "empty queries to f points mclk %d gpc2clk %d", table->mclk_num_points, table->gpc2clk_num_points); status = -EINVAL; goto exit_vf_table; @@ -749,15 +744,13 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) p5_info = pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P5, clkwhich_mclk); if (!p5_info) { - gk20a_err(dev_from_gk20a(g), - "failed to get MCLK P5 info"); + nvgpu_err(g, "failed to get MCLK P5 info"); goto exit_vf_table; } p0_info = pstate_get_clk_set_info(g, CTRL_PERF_PSTATE_P0, clkwhich_mclk); if (!p0_info) { - gk20a_err(dev_from_gk20a(g), - "failed to get MCLK P0 info"); + nvgpu_err(g, "failed to get MCLK P0 info"); goto exit_vf_table; } @@ -775,7 +768,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) &table->mclk_points[j].mem_mhz, &mclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); if (status < 0) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "failed to get MCLK LOGIC voltage"); goto exit_vf_table; } @@ -784,8 +777,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) &mclk_voltuv_sram, CTRL_VOLT_DOMAIN_SRAM); if (status < 0) { - gk20a_err(dev_from_gk20a(g), - "failed to get MCLK SRAM voltage"); + nvgpu_err(g, "failed to get MCLK SRAM voltage"); goto exit_vf_table; } @@ -815,8 +807,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) CTRL_PERF_PSTATE_P5, clkwhich_gpc2clk); if (!p5_info) { status = -EINVAL; - gk20a_err(dev_from_gk20a(g), - "failed to get GPC2CLK P5 info"); + nvgpu_err(g, "failed to get GPC2CLK P5 info"); goto exit_vf_table; } @@ -824,8 +815,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) CTRL_PERF_PSTATE_P0, clkwhich_gpc2clk); if (!p0_info) { status = -EINVAL; - gk20a_err(dev_from_gk20a(g), - "failed to get GPC2CLK P0 info"); + nvgpu_err(g, "failed to get GPC2CLK P0 info"); goto exit_vf_table; } @@ -847,7 +837,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) setfllclk.gpc2clkmhz = arb->gpc2clk_f_points[i]; status = clk_get_fll_clks(g, &setfllclk); if (status < 0) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "failed to get GPC2CLK slave clocks"); goto exit_vf_table; } @@ -888,8 +878,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) clkwhich_sys2clk); if (!p5_info) { status = -EINVAL; - gk20a_err(dev_from_gk20a(g), - "failed to get SYS2CLK P5 info"); + nvgpu_err(g, "failed to get SYS2CLK P5 info"); goto exit_vf_table; } @@ -915,8 +904,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) } /* no VF exists that satisfies condition */ if (j == table->gpc2clk_num_points) { - gk20a_err(dev_from_gk20a(g), - "NO SYS2CLK VF point possible"); + nvgpu_err(g, "NO SYS2CLK VF point possible"); status = -EINVAL; goto exit_vf_table; } @@ -928,8 +916,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) clkwhich_xbar2clk); if (!p5_info) { status = -EINVAL; - gk20a_err(dev_from_gk20a(g), - "failed to get SYS2CLK P5 info"); + nvgpu_err(g, "failed to get SYS2CLK P5 info"); goto exit_vf_table; } @@ -954,8 +941,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) /* no VF exists that satisfies condition */ if (j == table->gpc2clk_num_points) { status = -EINVAL; - gk20a_err(dev_from_gk20a(g), - "NO XBAR2CLK VF point possible"); + nvgpu_err(g, "NO XBAR2CLK VF point possible"); goto exit_vf_table; } @@ -966,8 +952,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) &alt_gpc2clk, &gpc2clk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); if (status < 0) { - gk20a_err(dev_from_gk20a(g), - "failed to get GPC2CLK LOGIC voltage"); + nvgpu_err(g, "failed to get GPC2CLK LOGIC voltage"); goto exit_vf_table; } @@ -976,8 +961,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) &gpc2clk_voltuv_sram, CTRL_VOLT_DOMAIN_SRAM); if (status < 0) { - gk20a_err(dev_from_gk20a(g), - "failed to get GPC2CLK SRAM voltage"); + nvgpu_err(g, "failed to get GPC2CLK SRAM voltage"); goto exit_vf_table; } @@ -1017,8 +1001,7 @@ static void nvgpu_clk_arb_run_vf_table_cb(struct work_struct *work) /* get latest vf curve from pmu */ err = clk_vf_point_cache(g); if (err) { - gk20a_err(dev_from_gk20a(g), - "failed to cache VF table"); + nvgpu_err(g, "failed to cache VF table"); nvgpu_clk_arb_set_global_alarm(g, EVENT(ALARM_VF_TABLE_UPDATE_FAILED)); if (arb->update_work_queue) @@ -1288,8 +1271,7 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work) exit_arb: if (status < 0) { - gk20a_err(dev_from_gk20a(g), - "Error in arbiter update"); + nvgpu_err(g, "Error in arbiter update"); nvgpu_clk_arb_set_global_alarm(g, EVENT(ALARM_CLOCK_ARBITER_FAILED)); } @@ -1856,7 +1838,7 @@ static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, if (!table) continue; if ((!table->gpc2clk_num_points) || (!table->mclk_num_points)) { - gk20a_err(dev_from_gk20a(arb->g), "found empty table"); + nvgpu_err(arb->g, "found empty table"); goto find_exit; } /* First we check MCLK to find out which PSTATE we are diff --git a/drivers/gpu/nvgpu/clk/clk_common.c b/drivers/gpu/nvgpu/clk/clk_common.c index 346ad12b..3230ded0 100644 --- a/drivers/gpu/nvgpu/clk/clk_common.c +++ b/drivers/gpu/nvgpu/clk/clk_common.c @@ -29,7 +29,7 @@ struct clk *gk20a_clk_get(struct gk20a *g) clk = clk_get_sys(clk_dev_id, "gpu"); if (IS_ERR(clk)) { - gk20a_err(dev, "fail to get tegra gpu clk %s/gpu\n", + nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n", clk_dev_id); return NULL; } diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index 2a614f55..c784bdb4 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c @@ -81,7 +81,7 @@ static u32 _clk_domains_pmudatainit_3x(struct gk20a *g, status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error updating pmu boardobjgrp for clk domain 0x%x", status); goto done; @@ -142,7 +142,7 @@ u32 clk_domain_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e32(&g->clk_pmu.clk_domainobjs.super); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error creating boardobjgrp for clk domain, status - 0x%x", status); goto done; @@ -156,7 +156,7 @@ u32 clk_domain_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_domain, CLK_DOMAIN); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -379,7 +379,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, break; default: - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error reading clock domain entry %d", index); status = -EINVAL; goto done; @@ -388,7 +388,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, pclkdomain_dev = construct_clk_domain(g, (void *)&clk_domain_data); if (pclkdomain_dev == NULL) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "unable to construct clock domain boardobj for %d", index); status = -EINVAL; @@ -397,7 +397,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, status = boardobjgrp_objinsert(&pclkdomainobjs->super.super, (struct boardobj *)pclkdomain_dev, index); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "unable to insert clock domain boardobj for %d", index); status = -EINVAL; goto done; @@ -1097,7 +1097,7 @@ u32 clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk) struct clk_domain *, pdomain, i) { status = pdomain->clkdomainclkproglink(g, pclk, pdomain); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error flattening VF for CLK DOMAIN - 0x%x", pdomain->domain); goto done; diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 7694e720..e097e593 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -45,7 +45,7 @@ static u32 _clk_fll_devgrp_pmudatainit_super(struct gk20a *g, status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); if (status) { - gk20a_err(dev_from_gk20a(g), "failed to init fll pmuobjgrp"); + nvgpu_err(g, "failed to init fll pmuobjgrp"); return status; } pset->lut_num_entries = pfll_objs->lut_num_entries; @@ -118,7 +118,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_fllobjs.super); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error creating boardobjgrp for fll, status - 0x%x", status); goto done; } @@ -130,7 +130,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_fll_device, CLK_FLL_DEVICE); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -155,7 +155,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) &g->clk_pmu.avfs_fllobjs.super.super, clk, CLK, clk_fll_device, CLK_FLL_DEVICE); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -179,7 +179,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) &pfllobjs->lut_prog_master_mask.super, BOARDOBJ_GET_IDX(pfll)); if (status) { - gk20a_err(dev_from_gk20a(g), "err setting lutprogmask"); + nvgpu_err(g, "err setting lutprogmask"); goto done; } pfll_master = pfll; @@ -188,7 +188,7 @@ u32 clk_fll_sw_setup(struct gk20a *g) g, pfllobjs, pfll_master, pfll); if (status) { - gk20a_err(dev_from_gk20a(g), "err setting lutslavemask"); + nvgpu_err(g, "err setting lutslavemask"); goto done; } } diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 4b47d978..61c8b81b 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c @@ -287,7 +287,7 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, (void *)&freq_controller_data); if (pclk_freq_cntr == NULL) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "unable to construct clock freq cntlr boardobj for %d", entry_idx); status = -EINVAL; @@ -298,7 +298,7 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, &pclk_freq_controllers->super.super, (struct boardobj *)pclk_freq_cntr, entry_idx); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "unable to insert clock freq cntlr boardobj for"); status = -EINVAL; goto done; @@ -363,7 +363,7 @@ static u32 _clk_freq_controllers_pmudatainit(struct gk20a *g, status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error updating pmu boardobjgrp for clk freq ctrs 0x%x", status); goto done; @@ -391,7 +391,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; status = boardobjgrpconstruct_e32(&pclk_freq_controllers->super); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error creating boardobjgrp for clk FCT, status - 0x%x", status); goto done; @@ -413,7 +413,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_freq_controller, CLK_FREQ_CONTROLLER); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -421,8 +421,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) status = clk_get_freq_controller_table(g, pclk_freq_controllers); if (status) { - gk20a_err(dev_from_gk20a(g), - "error reading freq controller table - 0x%x", + nvgpu_err(g, "error reading freq controller table - 0x%x", status); goto done; } diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index f973a696..690f8681 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c @@ -1979,7 +1979,7 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg, gk20a_dbg_info(""); if (status != 0) { - gk20a_err(dev_from_gk20a(g), "mclk seq_script cmd aborted"); + nvgpu_err(g, "mclk seq_script cmd aborted"); msg_status = -ENOENT; goto status_update; } @@ -2088,8 +2088,7 @@ static int mclk_get_memclk_table(struct gk20a *g) } if (shadow_idx > fb_fbpa_fbio_delay_priv_max_v()) { - gk20a_err(dev_from_gk20a(g), - "invalid shadow reg script index"); + nvgpu_err(g, "invalid shadow reg script index"); status = -EINVAL; goto done; } @@ -2140,8 +2139,8 @@ static int mclk_get_memclk_table(struct gk20a *g) } if (cmd_idx > fb_fbpa_fbio_cmd_delay_cmd_priv_max_v()) { - gk20a_err(dev_from_gk20a(g), - "invalid shadow reg cmd script index"); + nvgpu_err(g, + "invalid shadow reg cmd script index"); status = -EINVAL; goto done; } @@ -2236,8 +2235,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g) mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); if (!mclk->vreg_buf) { - gk20a_err(dev_from_gk20a(g), - "unable to allocate memory for VREG"); + nvgpu_err(g, "unable to allocate memory for VREG"); err = -ENOMEM; goto fail_data_mutex; } @@ -2318,8 +2316,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) } break; default: - gk20a_err(dev_from_gk20a(g), - "Illegal MCLK clock change"); + nvgpu_err(g, "Illegal MCLK clock change"); status = -EINVAL; goto exit_status; } @@ -2368,8 +2365,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) mclk_seq_pmucmdhandler, &seq_completion_status, &seqdesc, ~0); if (status) { - gk20a_err(dev_from_gk20a(g), - "unable to post seq script exec cmd for unit %x ", + nvgpu_err(g, "unable to post seq script exec cmd for unit %x", cmd.hdr.unit_id); goto exit_status; } @@ -2377,8 +2373,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), &seq_completion_status, 0); if (seq_completion_status != 0) { - gk20a_err(dev_from_gk20a(g), - "seq_script update failed"); + nvgpu_err(g, "seq_script update failed"); status = -EBUSY; goto exit_status; } diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index dc9c58a6..5697c255 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c @@ -46,8 +46,7 @@ static u32 _clk_progs_pmudatainit(struct gk20a *g, status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); if (status) { - gk20a_err(dev_from_gk20a(g), - "error updating pmu boardobjgrp for clk prog 0x%x", + nvgpu_err(g, "error updating pmu boardobjgrp for clk prog 0x%x", status); goto done; } @@ -89,7 +88,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_progobjs.super); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error creating boardobjgrp for clk prog, status - 0x%x", status); goto done; @@ -103,7 +102,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_prog, CLK_PROG); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -118,8 +117,7 @@ u32 clk_prog_sw_setup(struct gk20a *g) status = clk_domain_clk_prog_link(g, &g->clk_pmu); if (status) { - gk20a_err(dev_from_gk20a(g), - "error constructing VF point board objects"); + nvgpu_err(g, "error constructing VF point board objects"); goto done; } @@ -265,8 +263,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, break; default: - gk20a_err(dev_from_gk20a(g), - "invalid source %d", prog_type); + nvgpu_err(g, "invalid source %d", prog_type); status = -EINVAL; goto done; } @@ -346,16 +343,15 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, default: - gk20a_err(dev_from_gk20a(g), - "source issue %d", prog_type); + nvgpu_err(g, "source issue %d", prog_type); status = -EINVAL; goto done; } pprog = construct_clk_prog(g, (void *)&prog_data); if (pprog == NULL) { - gk20a_err(dev_from_gk20a(g), - "error constructing clk_prog boardobj %d", i); + nvgpu_err(g, + "error constructing clk_prog boardobj %d", i); status = -EINVAL; goto done; } @@ -363,8 +359,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g, status = boardobjgrp_objinsert(&pclkprogobjs->super.super, (struct boardobj *)pprog, i); if (status) { - gk20a_err(dev_from_gk20a(g), - "error adding clk_prog boardobj %d", i); + nvgpu_err(g, "error adding clk_prog boardobj %d", i); status = -EINVAL; goto done; } @@ -930,7 +925,7 @@ static u32 vflookup_prog_1x_master for (j = pvfentry->vf_point_idx_first; j <= pvfentry->vf_point_idx_last; j++) { pvfpoint = CLK_CLK_VF_POINT_GET(pclk, j); - gk20a_err(dev_from_gk20a(g), "v %x c %x", + nvgpu_err(g, "v %x c %x", clkvfpointvoltageuvget(g, pvfpoint), clkvfpointfreqmhzget(g, pvfpoint)); } diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index f4019f9d..3ec111f0 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c @@ -31,7 +31,7 @@ static u32 _clk_vf_points_pmudatainit(struct gk20a *g, status = boardobjgrp_pmudatainit_e32(g, pboardobjgrp, pboardobjgrppmu); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error updating pmu boardobjgrp for clk vfpoint 0x%x", status); goto done; @@ -90,7 +90,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e255(&g->clk_pmu.clk_vf_pointobjs.super); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error creating boardobjgrp for clk vfpoint, status - 0x%x", status); goto done; @@ -104,7 +104,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_vf_point, CLK_VF_POINT); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -114,7 +114,7 @@ u32 clk_vf_point_sw_setup(struct gk20a *g) &g->clk_pmu.clk_vf_pointobjs.super.super, clk, CLK, clk_vf_point, CLK_VF_POINT); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -356,7 +356,7 @@ static u32 clk_vf_point_update(struct gk20a *g, ppmudata; if (pstatus->super.type != pclk_vf_point->super.type) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "pmu data and boardobj type not matching"); return -EINVAL; } @@ -386,7 +386,7 @@ u32 clk_vf_point_cache(struct gk20a *g) status = pboardobjgrp->pmugetstatus(g, pboardobjgrp, pboardobjgrpmask); if (status) { - gk20a_err(dev_from_gk20a(g), "err getting boardobjs from pmu"); + nvgpu_err(g, "err getting boardobjs from pmu"); return status; } pboardobjgrppmu = pboardobjgrp->pmu.getstatus.buf; @@ -396,16 +396,14 @@ u32 clk_vf_point_cache(struct gk20a *g) (struct nv_pmu_boardobjgrp *)pboardobjgrppmu, &pboardobjpmustatus, index); if (status) { - gk20a_err(dev_from_gk20a(g), - "could not get status object instance"); + nvgpu_err(g, "could not get status object instance"); return status; } status = clk_vf_point_update(g, pboardobj, (struct nv_pmu_boardobj *)pboardobjpmustatus); if (status) { - gk20a_err(dev_from_gk20a(g), - "invalid data from pmu at %d", index); + nvgpu_err(g, "invalid data from pmu at %d", index); return status; } } diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index af388671..0fceb89d 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c @@ -252,7 +252,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) status = boardobjgrpconstruct_e32(&g->clk_pmu.avfs_vinobjs.super); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error creating boardobjgrp for clk vin, statu - 0x%x", status); goto done; @@ -266,7 +266,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp, clk, CLK, clk_vin_device, CLK_VIN_DEVICE); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; @@ -290,7 +290,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) status = read_vin_cal_slope_intercept_fuse(g, pvindev->id, &slope, &intercept); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "err reading vin cal for id %x", pvindev->id); goto done; } @@ -304,7 +304,7 @@ u32 clk_vin_sw_setup(struct gk20a *g) &g->clk_pmu.avfs_vinobjs.super.super, clk, CLK, clk_vin_device, CLK_VIN_DEVICE); if (status) { - gk20a_err(dev_from_gk20a(g), + nvgpu_err(g, "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x", status); goto done; -- cgit v1.2.2