From 8a4e6945302e35204eac1dd1c88cac615825217a Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Tue, 24 Apr 2018 11:32:43 +0530 Subject: gpu: nvgpu: effective freq load changes Read clk frequency through PMU RPC Bug 200399373 Change-Id: I9e887dcb1c5b622110eb4c1584f2f34434efd674 Signed-off-by: Vaikundanathan S Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1701276 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk_fll.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/clk/clk_fll.c') diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index 87222b90..a05fdf22 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -340,6 +340,7 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, CTRL_CLK_FLL_REGIME_ID_FFR; fll_dev_data.regime_desc.fixed_freq_regime_limit_mhz = (u16)fll_desc_table_entry.ffr_cutoff_freq_mhz; + fll_dev_data.regime_desc.target_regime_id_override=0; /*construct fll device*/ pfll_dev = construct_fll_device(g, (void *)&fll_dev_data); -- cgit v1.2.2