From a02e1c1f0b012b743d4c1ba9c853057b4359107e Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Fri, 13 Jul 2018 15:24:04 +0530 Subject: nvgpu:ps35: Clock domain changes 1. PMU interface changes 2. Split PS3.0 and PS3.5 into two dev init functions. 3. Split construct and pmu_data_init to two funcitons. 4. Fixing GV100 impact on PS3.5 changes Change-Id: I46ba80325d4a249918edbe4cf868ddf47c778aa1 Signed-off-by: Vaikundanathan S Reviewed-on: https://git-master.nvidia.com/r/1777739 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk_domain.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'drivers/gpu/nvgpu/clk/clk_domain.h') diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h index d0170339..a8ae0d48 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/clk/clk_domain.h @@ -112,17 +112,42 @@ struct clk_domain_3x_prog { u8 noise_aware_ordering_index; }; +struct clk_domain_35_prog { + struct clk_domain_3x_prog super; + u8 pre_volt_ordering_index; + u8 post_volt_ordering_index; + u8 clk_pos; + u8 clk_vf_curve_count; +}; + struct clk_domain_3x_master { struct clk_domain_3x_prog super; u32 slave_idxs_mask; }; +struct clk_domain_35_master { + struct clk_domain_35_prog super; + struct clk_domain_3x_master master; + struct boardobjgrpmask_e32 master_slave_domains_grp_mask; +}; + struct clk_domain_3x_slave { struct clk_domain_3x_prog super; u8 master_idx; clkgetslaveclk *clkdomainclkgetslaveclk; }; +struct clk_domain_30_slave { + u8 rsvd; + u8 master_idx; + clkgetslaveclk *clkdomainclkgetslaveclk; +}; + +struct clk_domain_35_slave { + struct clk_domain_35_prog super; + struct clk_domain_30_slave slave; +}; + int clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk); #define CLK_CLK_DOMAIN_GET(pclk, idx) \ -- cgit v1.2.2