From 8a4e6945302e35204eac1dd1c88cac615825217a Mon Sep 17 00:00:00 2001
From: Vaikundanathan S <vaikuns@nvidia.com>
Date: Tue, 24 Apr 2018 11:32:43 +0530
Subject: gpu: nvgpu: effective freq load changes

Read clk frequency through PMU RPC

Bug 200399373

Change-Id: I9e887dcb1c5b622110eb4c1584f2f34434efd674
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1701276
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/clk/clk.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'drivers/gpu/nvgpu/clk/clk.h')

diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h
index 70b04fc4..cd65f6f5 100644
--- a/drivers/gpu/nvgpu/clk/clk.h
+++ b/drivers/gpu/nvgpu/clk/clk.h
@@ -143,4 +143,6 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
 	struct nv_pmu_clk_rpc *rpccall,
 	struct set_fll_clk *setfllclk);
 u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
+int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload);
+u32 clk_freq_effective_avg(struct gk20a *g, u32  clkDomainMask);
 #endif
-- 
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