From 20b746b485be79abd0b9d1aedc8fb9cd741e5183 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Fri, 28 Jul 2017 12:20:52 +0530 Subject: gpu: nvgpu: Selectively disable/enable CFC clk_pmu_freq_controller_load used the default mask and affected all the clock frequency controllers (CFC) which had their bits set in the mask. We wish to enable/disable the CFCs in isolation through debugfs. So we add a parameter(bit_idx) to the function which will help affect only one CFC at a time JIRA DNVGPU-207 DEPENDS ON: Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/1563303 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/clk/clk.h') diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h index d2f615bc..a19e2e77 100644 --- a/drivers/gpu/nvgpu/clk/clk.h +++ b/drivers/gpu/nvgpu/clk/clk.h @@ -126,5 +126,5 @@ u32 clk_domain_get_f_points( ); int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); -int clk_pmu_freq_controller_load(struct gk20a *g, bool bload); +int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx); #endif -- cgit v1.2.2