From f9e55fbaf66c024125a19e1a773a1a4f0e9648f4 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 7 May 2018 11:42:33 +0530 Subject: gpu: nvgpu: Add LDIV slowdown factor in INIT cmd. PMU ucode is updated to include LDIV slowdown factor in gr_init_param command. - Defined a new version gr_init_param_v2. - Updated the PMU FW version code. - Set the LDIV slowdown factor to 0x1e by default. - Added sysfs entry to program ldiv_slowdown factor at runtime. Bug 200391931 Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1674208 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/driver_common.c | 1 + drivers/gpu/nvgpu/common/linux/platform_gk20a.h | 3 ++ .../gpu/nvgpu/common/linux/platform_gp10b_tegra.c | 3 ++ drivers/gpu/nvgpu/common/linux/sysfs.c | 55 ++++++++++++++++++- drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 2 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 12 +++-- drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | 61 +++++++++++++++++++++- 8 files changed, 130 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c index c3663117..53789423 100644 --- a/drivers/gpu/nvgpu/common/linux/driver_common.c +++ b/drivers/gpu/nvgpu/common/linux/driver_common.c @@ -159,6 +159,7 @@ static void nvgpu_init_pm_vars(struct gk20a *g) g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g)); g->can_railgate = platform->can_railgate_init; g->railgate_delay = platform->railgate_delay_init; + g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init; __nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon); /* set default values to aelpg parameters */ diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h index 43afbbf9..dec79b87 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h @@ -74,6 +74,9 @@ struct gk20a_platform { /* Delay before rail gated */ int railgate_delay_init; + /* init value for slowdown factor */ + u8 ldiv_slowdown_factor_init; + /* Second Level Clock Gating: true = enable false = disable */ bool enable_slcg; diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c index 96acf24b..6e54d00b 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c @@ -370,6 +370,9 @@ struct gk20a_platform gp10b_tegra_platform = { /* power management configuration */ .railgate_delay_init = 500, + /* ldiv slowdown factor */ + .ldiv_slowdown_factor_init = SLOWDOWN_FACTOR_FPDIV_BY16, + /* power management configuration */ .can_railgate_init = true, .enable_elpg = true, diff --git a/drivers/gpu/nvgpu/common/linux/sysfs.c b/drivers/gpu/nvgpu/common/linux/sysfs.c index 6709285d..1f6da803 100644 --- a/drivers/gpu/nvgpu/common/linux/sysfs.c +++ b/drivers/gpu/nvgpu/common/linux/sysfs.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -504,6 +504,58 @@ static ssize_t elpg_enable_read(struct device *dev, static DEVICE_ATTR(elpg_enable, ROOTRW, elpg_enable_read, elpg_enable_store); +static ssize_t ldiv_slowdown_factor_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct gk20a *g = get_gk20a(dev); + unsigned long val = 0; + int err; + + if (kstrtoul(buf, 10, &val) < 0) { + nvgpu_err(g, "parse error for input SLOWDOWN factor\n"); + return -EINVAL; + } + + if (val >= SLOWDOWN_FACTOR_FPDIV_BYMAX) { + nvgpu_err(g, "Invalid SLOWDOWN factor\n"); + return -EINVAL; + } + + if (val == g->ldiv_slowdown_factor) + return count; + + if (!g->power_on) { + g->ldiv_slowdown_factor = val; + } else { + err = gk20a_busy(g); + if (err) + return -EAGAIN; + + g->ldiv_slowdown_factor = val; + + if (g->ops.pmu.pmu_pg_init_param) + g->ops.pmu.pmu_pg_init_param(g, + PMU_PG_ELPG_ENGINE_ID_GRAPHICS); + + gk20a_idle(g); + } + + nvgpu_info(g, "ldiv_slowdown_factor is %x\n", g->ldiv_slowdown_factor); + + return count; +} + +static ssize_t ldiv_slowdown_factor_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gk20a *g = get_gk20a(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", g->ldiv_slowdown_factor); +} + +static DEVICE_ATTR(ldiv_slowdown_factor, ROOTRW, + ldiv_slowdown_factor_read, ldiv_slowdown_factor_store); + static ssize_t mscg_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -1114,6 +1166,7 @@ int nvgpu_create_sysfs(struct device *dev) error |= device_create_file(dev, &dev_attr_elpg_enable); error |= device_create_file(dev, &dev_attr_mscg_enable); error |= device_create_file(dev, &dev_attr_emc3d_ratio); + error |= device_create_file(dev, &dev_attr_ldiv_slowdown_factor); #ifdef CONFIG_TEGRA_DVFS error |= device_create_file(dev, &dev_attr_fmax_at_vmin_safe); #endif diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index ed4e6c20..c610c391 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -39,7 +39,7 @@ #define APP_VERSION_GV11B 23416738 #define APP_VERSION_GV10X 23616379 #define APP_VERSION_GP10X 24008084 -#define APP_VERSION_GP10B 20429989 +#define APP_VERSION_GP10B 23782727 #define APP_VERSION_GM20B 20490253 /* PMU version specific functions */ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index bf2e0dbb..476c1dd3 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1333,7 +1333,7 @@ struct gk20a { bool can_railgate; bool user_railgate_disabled; int railgate_delay; - + u8 ldiv_slowdown_factor; unsigned int aggressive_sync_destroy_thresh; bool aggressive_sync_destroy; diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 49ad3920..c94d580a 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B PMU * - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -233,13 +233,15 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) memset(&cmd, 0, sizeof(struct pmu_cmd)); cmd.hdr.unit_id = PMU_UNIT_PG; cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_pg_cmd_gr_init_param); - cmd.cmd.pg.gr_init_param.cmd_type = + sizeof(struct pmu_pg_cmd_gr_init_param_v2); + cmd.cmd.pg.gr_init_param_v2.cmd_type = PMU_PG_CMD_ID_PG_PARAM; - cmd.cmd.pg.gr_init_param.sub_cmd_id = + cmd.cmd.pg.gr_init_param_v2.sub_cmd_id = PMU_PG_PARAM_CMD_GR_INIT_PARAM; - cmd.cmd.pg.gr_init_param.featuremask = + cmd.cmd.pg.gr_init_param_v2.featuremask = NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; + cmd.cmd.pg.gr_init_param_v2.ldiv_slowdown_factor = + g->ldiv_slowdown_factor; gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h index 91656156..1ba9963c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -122,6 +122,57 @@ enum { PMU_PG_STAT_CMD_ALLOC_DMEM = 0, }; +enum { + SLOWDOWN_FACTOR_FPDIV_BY1 = 0, + SLOWDOWN_FACTOR_FPDIV_BY1P5, + SLOWDOWN_FACTOR_FPDIV_BY2, + SLOWDOWN_FACTOR_FPDIV_BY2P5, + SLOWDOWN_FACTOR_FPDIV_BY3, + SLOWDOWN_FACTOR_FPDIV_BY3P5, + SLOWDOWN_FACTOR_FPDIV_BY4, + SLOWDOWN_FACTOR_FPDIV_BY4P5, + SLOWDOWN_FACTOR_FPDIV_BY5, + SLOWDOWN_FACTOR_FPDIV_BY5P5, + SLOWDOWN_FACTOR_FPDIV_BY6, + SLOWDOWN_FACTOR_FPDIV_BY6P5, + SLOWDOWN_FACTOR_FPDIV_BY7, + SLOWDOWN_FACTOR_FPDIV_BY7P5, + SLOWDOWN_FACTOR_FPDIV_BY8, + SLOWDOWN_FACTOR_FPDIV_BY8P5, + SLOWDOWN_FACTOR_FPDIV_BY9, + SLOWDOWN_FACTOR_FPDIV_BY9P5, + SLOWDOWN_FACTOR_FPDIV_BY10, + SLOWDOWN_FACTOR_FPDIV_BY10P5, + SLOWDOWN_FACTOR_FPDIV_BY11, + SLOWDOWN_FACTOR_FPDIV_BY11P5, + SLOWDOWN_FACTOR_FPDIV_BY12, + SLOWDOWN_FACTOR_FPDIV_BY12P5, + SLOWDOWN_FACTOR_FPDIV_BY13, + SLOWDOWN_FACTOR_FPDIV_BY13P5, + SLOWDOWN_FACTOR_FPDIV_BY14, + SLOWDOWN_FACTOR_FPDIV_BY14P5, + SLOWDOWN_FACTOR_FPDIV_BY15, + SLOWDOWN_FACTOR_FPDIV_BY15P5, + SLOWDOWN_FACTOR_FPDIV_BY16, + SLOWDOWN_FACTOR_FPDIV_BY16P5, + SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20, + SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22, + SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24, + SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26, + SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28, + SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a, + SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c, + SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e, + SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30, + SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32, + SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34, + SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36, + SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38, + SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a, + SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c, + SLOWDOWN_FACTOR_FPDIV_BYMAX, +}; + #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 #define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 #define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 @@ -212,6 +263,13 @@ struct pmu_pg_cmd_gr_init_param { u8 featuremask; }; +struct pmu_pg_cmd_gr_init_param_v2 { + u8 cmd_type; + u16 sub_cmd_id; + u8 featuremask; + u8 ldiv_slowdown_factor; +}; + struct pmu_pg_cmd_gr_init_param_v1 { u8 cmd_type; u16 sub_cmd_id; @@ -277,6 +335,7 @@ struct pmu_pg_cmd { struct pmu_pg_cmd_stat stat; struct pmu_pg_cmd_gr_init_param gr_init_param; struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1; + struct pmu_pg_cmd_gr_init_param_v2 gr_init_param_v2; struct pmu_pg_cmd_ms_init_param ms_init_param; struct pmu_pg_cmd_mclk_change mclk_change; struct pmu_pg_cmd_post_init_param post_init; -- cgit v1.2.2