From f99de40936236b4e8b00fa847f502c7b94af85c3 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 2 Jun 2016 17:38:37 +0530 Subject: gpu: nvgpu: WPR & PMU interface update Update WPR interface & PMU interface to support latest ACR/PMU ucode versions Change-Id: I4d1bd7a5c43751e96c1db58832cd316006d56954 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1158070 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 ++-- drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 4 ++-- drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 32 ++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 40 +++++++++++++++++++------------------ drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 6 ++++++ 5 files changed, 62 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 85289087..3da19cc8 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -549,10 +549,10 @@ struct gpu_ops { int (*falcon_clear_halt_interrupt_status)(struct gk20a *g, unsigned int timeout); int (*init_falcon_setup_hw)(struct gk20a *g, - struct flcn_bl_dmem_desc *desc, u32 bl_sz); + void *desc, u32 bl_sz); bool (*is_lazy_bootstrap)(u32 falcon_id); bool (*is_priv_load)(u32 falcon_id); - void (*get_wpr)(struct gk20a *g, u64 *base, u64 *size); + void (*get_wpr)(struct gk20a *g, struct wpr_carveout_info *inf); int (*alloc_blob_space)(struct gk20a *g, size_t size, struct mem_desc *mem); int (*pmu_populate_loader_cfg)(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 51ffc552..d12c5987 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -1623,7 +1623,7 @@ void pmu_copy_to_dmem(struct pmu_gk20a *pmu, return; } -static int pmu_idle(struct pmu_gk20a *pmu) +int pmu_idle(struct pmu_gk20a *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); unsigned long end_jiffies = jiffies + @@ -1714,7 +1714,7 @@ void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) gk20a_dbg_fn("done"); } -static int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) +int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) { struct gk20a *g = gk20a_from_pmu(pmu); diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index b8bb18a2..7d91b111 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -450,6 +450,31 @@ struct pmu_ucode_desc { u32 compressed; }; +struct pmu_ucode_desc_v1 { + u32 descriptor_size; + u32 image_size; + u32 tools_version; + u32 app_version; + char date[GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH]; + u32 bootloader_start_offset; + u32 bootloader_size; + u32 bootloader_imem_offset; + u32 bootloader_entry_point; + u32 app_start_offset; + u32 app_size; + u32 app_imem_offset; + u32 app_imem_entry; + u32 app_dmem_offset; + u32 app_resident_code_offset; + u32 app_resident_code_size; + u32 app_resident_data_offset; + u32 app_resident_data_size; + u32 nb_imem_overlays; + u32 nb_dmem_overlays; + struct {u32 start; u32 size; } load_ovl[64]; + u32 compressed; +}; + #define PMU_UNIT_REWIND (0x00) #define PMU_UNIT_PG (0x03) #define PMU_UNIT_INIT (0x07) @@ -1295,7 +1320,10 @@ struct pmu_pg_stats { struct pmu_gk20a { - struct pmu_ucode_desc *desc; + union { + struct pmu_ucode_desc *desc; + struct pmu_ucode_desc_v1 *desc_v1; + }; struct mem_desc ucode; struct mem_desc pg_buf; @@ -1427,5 +1455,7 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); int gk20a_pmu_reset(struct gk20a *g); +int pmu_idle(struct pmu_gk20a *pmu); +int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable); #endif /*__PMU_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 1b8e7b5f..7ef6be09 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c @@ -43,7 +43,7 @@ static int gm20b_bootstrap_hs_flcn(struct gk20a *g); static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout); static int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); static int gm20b_init_pmu_setup_hw1(struct gk20a *g, - struct flcn_bl_dmem_desc *desc, u32 bl_sz); + void *desc, u32 bl_sz); static int lsfm_discover_ucode_images(struct gk20a *g, struct ls_flcn_mgr *plsfm); static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm, @@ -62,7 +62,7 @@ static int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct mem_desc *mem); static bool gm20b_is_priv_load(u32 falcon_id); static bool gm20b_is_lazy_bootstrap(u32 falcon_id); -static void gm20b_wpr_info(struct gk20a *g, u64 *base, u64 *size); +static void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); /*Globals*/ static get_ucode_details pmu_acr_supp_ucode_list[] = { @@ -83,13 +83,15 @@ static void start_gm20b_pmu(struct gk20a *g) pwr_falcon_cpuctl_startcpu_f(1)); } -static void gm20b_wpr_info(struct gk20a *g, u64 *base, u64 *size) +static void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) { - struct mc_carveout_info inf; + struct mc_carveout_info mem_inf; - mc_get_carveout_info(&inf, NULL, MC_SECURITY_CARVEOUT2); - *base = inf.base; - *size = inf.size; + mc_get_carveout_info(&mem_inf, NULL, MC_SECURITY_CARVEOUT2); + + inf->wpr_base = mem_inf.base; + inf->nonwpr_base = 0; + inf->size = mem_inf.size; } void gm20b_init_secure_pmu(struct gpu_ops *gops) @@ -368,7 +370,7 @@ int prepare_ucode_blob(struct gk20a *g) u32 wprsize; struct mm_gk20a *mm = &g->mm; struct vm_gk20a *vm = &mm->pmu.vm; - struct mc_carveout_info inf; + struct wpr_carveout_info wpr_inf; struct sg_table *sgt; struct page *page; @@ -388,10 +390,10 @@ int prepare_ucode_blob(struct gk20a *g) gm20b_mm_mmu_vpr_info_fetch(g); gr_gk20a_init_ctxsw_ucode(g); - g->ops.pmu.get_wpr(g, &inf.base, &inf.size); - wpr_addr = (phys_addr_t)inf.base; - wprsize = (u32)inf.size; - gm20b_dbg_pmu("wpr carveout base:%llx\n", inf.base); + g->ops.pmu.get_wpr(g, &wpr_inf); + wpr_addr = (phys_addr_t)wpr_inf.wpr_base; + wprsize = (u32)wpr_inf.size; + gm20b_dbg_pmu("wpr carveout base:%llx\n", wpr_inf.wpr_base); gm20b_dbg_pmu("wpr carveout size :%x\n", wprsize); sgt = kzalloc(sizeof(*sgt), GFP_KERNEL); @@ -539,7 +541,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g, static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size) { - struct mc_carveout_info inf; + struct wpr_carveout_info wpr_inf; struct pmu_gk20a *pmu = &g->pmu; struct lsfm_managed_ucode_img *p_lsfm = (struct lsfm_managed_ucode_img *)lsfm; @@ -563,8 +565,8 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, physical addresses of each respective segment. */ addr_base = p_lsfm->lsb_header.ucode_off; - g->ops.pmu.get_wpr(g, &inf.base, &inf.size); - addr_base += inf.base; + g->ops.pmu.get_wpr(g, &wpr_inf); + addr_base += wpr_inf.wpr_base; gm20b_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base); /*From linux*/ addr_code = u64_lo32((addr_base + @@ -611,7 +613,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g, static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid) { - struct mc_carveout_info inf; + struct wpr_carveout_info wpr_inf; struct lsfm_managed_ucode_img *p_lsfm = (struct lsfm_managed_ucode_img *)lsfm; struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img); @@ -635,11 +637,11 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, physical addresses of each respective segment. */ addr_base = p_lsfm->lsb_header.ucode_off; - g->ops.pmu.get_wpr(g, &inf.base, &inf.size); + g->ops.pmu.get_wpr(g, &wpr_inf); if (falconid == LSF_FALCON_ID_GPCCS) addr_base += g->pmu.wpr_buf.gpu_va; else - addr_base += inf.base; + addr_base += wpr_inf.wpr_base; gm20b_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, p_lsfm->wpr_header.falcon_id); addr_code = u64_lo32((addr_base + @@ -1299,7 +1301,7 @@ int gm20b_init_nspmu_setup_hw1(struct gk20a *g) } static int gm20b_init_pmu_setup_hw1(struct gk20a *g, - struct flcn_bl_dmem_desc *desc, u32 bl_sz) + void *desc, u32 bl_sz) { struct pmu_gk20a *pmu = &g->pmu; diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index a1dceae9..51492827 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h @@ -386,6 +386,12 @@ struct acr_fw_header { u32 hdr_size; /*size of above header*/ }; +struct wpr_carveout_info { + u64 wpr_base; + u64 nonwpr_base; + u64 size; +}; + void gm20b_init_secure_pmu(struct gpu_ops *gops); int prepare_ucode_blob(struct gk20a *g); int gm20b_pmu_setup_sw(struct gk20a *g); -- cgit v1.2.2