From f69682cda8ae3d6fd1825258b6664d580fecbf4d Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Wed, 3 Sep 2014 12:59:56 -0700 Subject: gpu: nvgpu: Bypass for GM20B post-divider change Switch GM20b GPCPLL under bypass when changing post-divider setting (for now, don't assume that post-divider is glitch-less). Change-Id: I62b1285c035de0913207a86c41f37b7765da3893 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/495300 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bo Yan --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 1b01c74c..86aa6e8b 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -78,7 +78,7 @@ static inline u32 div_to_pl(u32 div) } /* FIXME: remove after on-silicon testing */ -#define PLDIV_GLITCHLESS 1 +#define PLDIV_GLITCHLESS 0 /* Calculate and update M/N/PL as well as pll->freq ref_clk_f = clk_in_f; -- cgit v1.2.2