From f0cbe19b12524f5df6466eaf86acbfb349def6b1 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 16 Jan 2018 03:07:37 -0800 Subject: gpu: nvgpu: add user API to get read-only syncpoint address map Add User space API NVGPU_AS_IOCTL_GET_SYNC_RO_MAP to get read-only syncpoint address map in user space We already map whole syncpoint shim to each address space with base address being vm->syncpt_ro_map_gpu_va This new API exposes this base GPU_VA address of syncpoint map, and unit size of each syncpoint to user space. User space can then calculate address of each syncpoint as syncpoint_address = base_gpu_va + (syncpoint_id * syncpoint_unit_size) Note that this syncpoint address is read_only, and should be only used for inserting semaphore acquires. Adding semaphore release with this address would result in MMU_FAULT Define new HAL g->ops.fifo.get_sync_ro_map and set this for all GPUs supported on Xavier SoC Bug 200327559 Change-Id: Ica0db48fc28fdd0ff2a5eb09574dac843dc5e4fd Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1649365 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/ioctl_as.c | 33 +++++++- .../nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + .../common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c | 93 +++++++++++++++------- .../common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h | 4 +- .../nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | 1 + drivers/gpu/nvgpu/common/mm/vm.c | 2 + drivers/gpu/nvgpu/gk20a/gk20a.h | 2 + drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 56 ++++++++++--- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/vm.h | 2 + include/uapi/linux/nvgpu.h | 10 ++- 16 files changed, 167 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_as.c b/drivers/gpu/nvgpu/common/linux/ioctl_as.c index 8aea3d22..c5769476 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_as.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_as.c @@ -1,7 +1,7 @@ /* * GK20A Address Spaces * - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -256,6 +256,33 @@ static int gk20a_as_ioctl_get_va_regions( return 0; } +static int nvgpu_as_ioctl_get_sync_ro_map( + struct gk20a_as_share *as_share, + struct nvgpu_as_get_sync_ro_map_args *args) +{ +#ifdef CONFIG_TEGRA_GK20A_NVHOST + struct vm_gk20a *vm = as_share->vm; + struct gk20a *g = gk20a_from_vm(vm); + u64 base_gpuva; + u32 sync_size; + int err = 0; + + if (!g->ops.fifo.get_sync_ro_map) + return -EINVAL; + + err = g->ops.fifo.get_sync_ro_map(vm, &base_gpuva, &sync_size); + if (err) + return err; + + args->base_gpuva = base_gpuva; + args->sync_size = sync_size; + + return err; +#else + return -EINVAL; +#endif +} + int gk20a_as_dev_open(struct inode *inode, struct file *filp) { struct nvgpu_os_linux *l; @@ -367,6 +394,10 @@ long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) err = gk20a_as_ioctl_map_buffer_batch(as_share, (struct nvgpu_as_map_buffer_batch_args *)buf); break; + case NVGPU_AS_IOCTL_GET_SYNC_RO_MAP: + err = nvgpu_as_ioctl_get_sync_ro_map(as_share, + (struct nvgpu_as_get_sync_ro_map_args *)buf); + break; default: err = -ENOTTY; break; diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 164ac3d2..39b92263 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c @@ -341,6 +341,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = NULL, #endif .resetup_ramfc = NULL, .device_info_fault_id = top_device_info_data_fault_id_enum_v, diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c index 134ca67a..af25e486 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -23,12 +23,52 @@ #include #ifdef CONFIG_TEGRA_GK20A_NVHOST + +static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) +{ + int err; + struct gk20a *g = gk20a_from_vm(vm); + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt; + + if (vm->syncpt_ro_map_gpu_va) + return 0; + + vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm, + g->syncpt_unit_size, + gmmu_page_size_kernel); + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "allocating read-only va space failed"); + return -ENOMEM; + } + + msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; + msg.handle = vgpu_get_handle(g); + p->as_handle = vm->handle; + p->gpu_va = vm->syncpt_ro_map_gpu_va; + p->len = g->syncpt_unit_size; + p->offset = 0; + p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(g, + "mapping read-only va space failed err %d", + err); + __nvgpu_vm_free_va(vm, vm->syncpt_ro_map_gpu_va, + gmmu_page_size_kernel); + vm->syncpt_ro_map_gpu_va = 0; + return err; + } + + return 0; +} + int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) { int err; struct gk20a *g = c->g; - struct vm_gk20a *vm = c->vm; struct tegra_vgpu_cmd_msg msg = {}; struct tegra_vgpu_map_syncpt_params *p = &msg.params.map_syncpt; @@ -37,34 +77,11 @@ int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, * All channels sharing same vm will share same ro mapping. * Create rw map for current channel sync point. */ - if (!vm->syncpt_ro_map_gpu_va) { - vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm, - g->syncpt_unit_size, - gmmu_page_size_kernel); - if (!vm->syncpt_ro_map_gpu_va) { - nvgpu_err(g, "allocating read-only va space failed"); - return -ENOMEM; - } - - msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; - msg.handle = vgpu_get_handle(g); - p->as_handle = c->vm->handle; - p->gpu_va = vm->syncpt_ro_map_gpu_va; - p->len = g->syncpt_unit_size; - p->offset = 0; - p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - err = err ? err : msg.ret; - if (err) { - nvgpu_err(g, - "mapping read-only va space failed err %d", - err); - __nvgpu_vm_free_va(c->vm, vm->syncpt_ro_map_gpu_va, - gmmu_page_size_kernel); - vm->syncpt_ro_map_gpu_va = 0; - return err; - } - } + nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock); + err = set_syncpt_ro_map_gpu_va_locked(c->vm); + nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock); + if (err) + return err; syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size, gmmu_page_size_kernel); @@ -92,6 +109,24 @@ int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, return 0; } + +int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size) +{ + struct gk20a *g = gk20a_from_vm(vm); + int err; + + nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock); + err = set_syncpt_ro_map_gpu_va_locked(vm); + nvgpu_mutex_release(&vm->syncpt_ro_map_lock); + if (err) + return err; + + *base_gpuva = vm->syncpt_ro_map_gpu_va; + *sync_size = g->syncpt_size; + + return 0; +} #endif /* CONFIG_TEGRA_GK20A_NVHOST */ int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h index c2e75680..66f482af 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,4 +22,6 @@ struct gk20a; int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g); int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf); +int vgpu_gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size); #endif diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index 8669bf0d..b9e44b03 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c @@ -385,6 +385,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = vgpu_gv11b_fifo_get_sync_ro_map, #endif .resetup_ramfc = NULL, .reschedule_runlist = NULL, diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index f2d04dab..e5ad22f3 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c @@ -459,6 +459,7 @@ int __nvgpu_vm_init(struct mm_gk20a *mm, vm->mapped_buffers = NULL; + nvgpu_mutex_init(&vm->syncpt_ro_map_lock); nvgpu_mutex_init(&vm->update_gmmu_lock); nvgpu_ref_init(&vm->ref); nvgpu_init_list_node(&vm->vm_area_list); @@ -614,6 +615,7 @@ static void __nvgpu_vm_remove(struct vm_gk20a *vm) nvgpu_mutex_release(&vm->update_gmmu_lock); + nvgpu_mutex_destroy(&vm->syncpt_ro_map_lock); nvgpu_kfree(g, vm); } diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 5e46344a..02c7d0d9 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -617,6 +617,8 @@ struct gpu_ops { bool wfi_cmd, struct priv_cmd_entry *cmd, u32 id, u64 gpu_va); u32 (*get_syncpt_incr_cmd_size)(bool wfi_cmd); + int (*get_sync_ro_map)(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size); #endif } fifo; struct pmu_v { diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 58367bcb..b3efdc8a 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -436,6 +436,7 @@ static const struct gpu_ops gm20b_ops = { .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = NULL, #endif }, .gr_ctx = { diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 77a1b8f6..502a6778 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -496,6 +496,7 @@ static const struct gpu_ops gp106_ops = { .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = NULL, #endif .resetup_ramfc = gp10b_fifo_resetup_ramfc, .device_info_fault_id = top_device_info_data_fault_id_enum_v, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 462943a0..91ebab55 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -469,6 +469,7 @@ static const struct gpu_ops gp10b_ops = { .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = NULL, #endif .resetup_ramfc = gp10b_fifo_resetup_ramfc, .device_info_fault_id = top_device_info_data_fault_id_enum_v, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f75e6ff9..c39b3444 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -511,6 +511,7 @@ static const struct gpu_ops gv100_ops = { .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, #endif .resetup_ramfc = NULL, .device_info_fault_id = top_device_info_data_fault_id_enum_v, diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 271dcc41..41d14a82 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1657,31 +1657,43 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, } #ifdef CONFIG_TEGRA_GK20A_NVHOST +static int set_syncpt_ro_map_gpu_va_locked(struct vm_gk20a *vm) +{ + struct gk20a *g = gk20a_from_vm(vm); + + if (vm->syncpt_ro_map_gpu_va) + return 0; + + vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(vm, + &g->syncpt_mem, g->syncpt_unit_size, + 0, gk20a_mem_flag_read_only, + false, APERTURE_SYSMEM); + + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "failed to ro map syncpt buffer"); + return -ENOMEM; + } + + return 0; +} + int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) { u32 nr_pages; int err = 0; struct gk20a *g = c->g; - struct vm_gk20a *vm = c->vm; /* * Add ro map for complete sync point shim range in vm * All channels sharing same vm will share same ro mapping. * Create rw map for current channel sync point */ - if (!vm->syncpt_ro_map_gpu_va) { - vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(c->vm, - &g->syncpt_mem, g->syncpt_unit_size, - 0, gk20a_mem_flag_read_only, - false, APERTURE_SYSMEM); - - if (!vm->syncpt_ro_map_gpu_va) { - nvgpu_err(g, "failed to ro map syncpt buffer"); - nvgpu_dma_free(g, &g->syncpt_mem); - err = -ENOMEM; - } - } + nvgpu_mutex_acquire(&c->vm->syncpt_ro_map_lock); + err = set_syncpt_ro_map_gpu_va_locked(c->vm); + nvgpu_mutex_release(&c->vm->syncpt_ro_map_lock); + if (err) + return err; nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); __nvgpu_mem_create_from_phys(g, syncpt_buf, @@ -1707,6 +1719,24 @@ void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, nvgpu_dma_free(c->g, syncpt_buf); } +int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size) +{ + struct gk20a *g = gk20a_from_vm(vm); + int err; + + nvgpu_mutex_acquire(&vm->syncpt_ro_map_lock); + err = set_syncpt_ro_map_gpu_va_locked(vm); + nvgpu_mutex_release(&vm->syncpt_ro_map_lock); + if (err) + return err; + + *base_gpuva = vm->syncpt_ro_map_gpu_va; + *sync_size = g->syncpt_size; + + return 0; +} + void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, struct priv_cmd_entry *cmd, u32 off, u32 id, u32 thresh, u64 gpu_va_base) diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index fc1ddf83..c0e6e5cd 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B Fifo * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -102,6 +102,8 @@ int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf); void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, struct nvgpu_mem *syncpt_buf); +int gv11b_fifo_get_sync_ro_map(struct vm_gk20a *vm, + u64 *base_gpuva, u32 *sync_size); void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, struct priv_cmd_entry *cmd, u32 off, u32 id, u32 thresh, u64 gpu_va_base); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 91d80080..72537b44 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -534,6 +534,7 @@ static const struct gpu_ops gv11b_ops = { .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, + .get_sync_ro_map = gv11b_fifo_get_sync_ro_map, #endif .resetup_ramfc = NULL, .device_info_fault_id = top_device_info_data_fault_id_enum_v, diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h index e5d0e197..a5a358ea 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h @@ -198,6 +198,8 @@ struct vm_gk20a { * Channels sharing same vm will also share same sync point ro map */ u64 syncpt_ro_map_gpu_va; + /* Protect allocation of sync point map */ + struct nvgpu_mutex syncpt_ro_map_lock; }; /* diff --git a/include/uapi/linux/nvgpu.h b/include/uapi/linux/nvgpu.h index 6821af07..41b4eb8d 100644 --- a/include/uapi/linux/nvgpu.h +++ b/include/uapi/linux/nvgpu.h @@ -1968,6 +1968,12 @@ struct nvgpu_as_map_buffer_batch_args { __u64 reserved; }; +struct nvgpu_as_get_sync_ro_map_args { + __u64 base_gpuva; + __u32 sync_size; + __u32 padding; +}; + #define NVGPU_AS_IOCTL_BIND_CHANNEL \ _IOWR(NVGPU_AS_IOCTL_MAGIC, 1, struct nvgpu_as_bind_channel_args) #define NVGPU32_AS_IOCTL_ALLOC_SPACE \ @@ -1990,9 +1996,11 @@ struct nvgpu_as_map_buffer_batch_args { _IOWR(NVGPU_AS_IOCTL_MAGIC, 10, struct nvgpu_as_map_buffer_compbits_args) #define NVGPU_AS_IOCTL_MAP_BUFFER_BATCH \ _IOWR(NVGPU_AS_IOCTL_MAGIC, 11, struct nvgpu_as_map_buffer_batch_args) +#define NVGPU_AS_IOCTL_GET_SYNC_RO_MAP \ + _IOR(NVGPU_AS_IOCTL_MAGIC, 12, struct nvgpu_as_get_sync_ro_map_args) #define NVGPU_AS_IOCTL_LAST \ - _IOC_NR(NVGPU_AS_IOCTL_MAP_BUFFER_BATCH) + _IOC_NR(NVGPU_AS_IOCTL_GET_SYNC_RO_MAP) #define NVGPU_AS_IOCTL_MAX_ARG_SIZE \ sizeof(struct nvgpu_as_map_buffer_ex_args) -- cgit v1.2.2