From edaf6188d54683bd955f1dc6673b3bb3ba18367e Mon Sep 17 00:00:00 2001 From: Sam Payne Date: Mon, 12 Jan 2015 14:24:55 -0800 Subject: gpu: nvgpu: enable ce2 interrupts enables non-blocking interrupts in ce2 all other ce2 interrupts are cleared and not handled. bug 200036089 Change-Id: I9f47b06c677c72ac523019e6a3f70fedd07830a2 Signed-off-by: Sam Payne Reviewed-on: http://git-master/r/671783 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 95 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 30 +++++++++++ drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h | 81 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 10 ++-- drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 6 ++- drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h | 81 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 6 +-- drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | 2 +- 11 files changed, 302 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/nvgpu/gk20a/ce2_gk20a.c create mode 100644 drivers/gpu/nvgpu/gk20a/ce2_gk20a.h create mode 100644 drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h create mode 100644 drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 4e2ce497..6632a43a 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -19,6 +19,7 @@ nvgpu-y := \ gk20a/gk20a.o \ gk20a/as_gk20a.o \ gk20a/ctrl_gk20a.o \ + gk20a/ce2_gk20a.o \ gk20a/fifo_gk20a.o \ gk20a/channel_gk20a.o \ gk20a/channel_sync_gk20a.o \ diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c new file mode 100644 index 00000000..75df4ce5 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -0,0 +1,95 @@ +/* + * GK20A Graphics Copy Engine (gr host) + * + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +/*TODO: remove uncecessary */ +#include +#include +#include +#include +#include +#include + +#include "gk20a.h" +#include "debug_gk20a.h" +#include "semaphore_gk20a.h" +#include "hw_ce2_gk20a.h" +#include "hw_pbdma_gk20a.h" +#include "hw_ccsr_gk20a.h" +#include "hw_ram_gk20a.h" +#include "hw_proj_gk20a.h" +#include "hw_top_gk20a.h" +#include "hw_mc_gk20a.h" +#include "hw_gr_gk20a.h" + +static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); + + /* wake theads waiting in this channel */ + gk20a_channel_semaphore_wakeup(g); + return ce2_intr_status_nonblockpipe_pending_f(); +} + +static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); + + return ce2_intr_status_blockpipe_pending_f(); +} + +static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); + + return ce2_intr_status_launcherr_pending_f(); +} + +void gk20a_ce2_isr(struct gk20a *g) +{ + u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); + + /* clear blocking interrupts: they exibit broken behavior */ + if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) + clear_intr |= ce2_blockpipe_isr(g, ce2_intr); + + if (ce2_intr & ce2_intr_status_launcherr_pending_f()) + clear_intr |= ce2_launcherr_isr(g, ce2_intr); + + gk20a_writel(g, ce2_intr_status_r(), clear_intr); + return; +} + +void gk20a_ce2_nonstall_isr(struct gk20a *g) +{ + u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r()); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); + + if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) + clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); + + gk20a_writel(g, ce2_intr_status_r(), clear_intr); + + return; +} + diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h new file mode 100644 index 00000000..0a9ec62a --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h @@ -0,0 +1,30 @@ +/* + * drivers/video/tegra/host/gk20a/fifo_gk20a.h + * + * GK20A graphics copy engine (gr host) + * + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __CE2_GK20A_H__ +#define __CE2_GK20A_H__ + +#include "channel_gk20a.h" +#include "tsg_gk20a.h" + +void gk20a_ce2_isr(struct gk20a *g); +void gk20a_ce2_nonstall_isr(struct gk20a *g); + +#endif /*__CE2_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 184ef168..3c1186ed 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -37,6 +37,7 @@ struct acr_gm20b; #include "as_gk20a.h" #include "clk_gk20a.h" +#include "ce2_gk20a.h" #include "fifo_gk20a.h" #include "tsg_gk20a.h" #include "gr_gk20a.h" diff --git a/drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h new file mode 100644 index 00000000..df1fa836 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce2_gk20a_h_ +#define _hw_ce2_gk20a_h_ + +static inline u32 ce2_intr_status_r(void) +{ + return 0x00106908; +} +static inline u32 ce2_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce2_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 1de9e794..38ffd524 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1302,6 +1302,10 @@ static inline u32 gr_ds_zbc_color_r_val_f(u32 v) { return (v & 0xffffffff) << 0; } +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} static inline u32 gr_ds_zbc_color_g_r(void) { return 0x00405808; @@ -1350,10 +1354,6 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { return 0x00000004; } -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028; -} static inline u32 gr_ds_zbc_z_r(void) { return 0x00405818; diff --git a/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h index 479db499..97517a77 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 899eeff7..9f9e756b 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c @@ -1,7 +1,7 @@ /* * GK20A memory interface * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -73,6 +73,8 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g) if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)) + gk20a_ce2_isr(g); if (mc_intr_0 & mc_intr_0_pfifo_pending_f()) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_0_pmu_pending_f()) @@ -107,6 +109,8 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g) gk20a_fifo_nonstall_isr(g); if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id)) + gk20a_ce2_nonstall_isr(g); gk20a_writel(g, mc_intr_en_1_r(), mc_intr_en_1_inta_hardware_f()); diff --git a/drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h new file mode 100644 index 00000000..ca0212f8 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce2_gm20b_h_ +#define _hw_ce2_gm20b_h_ + +static inline u32 ce2_intr_status_r(void) +{ + return 0x00106908; +} +static inline u32 ce2_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce2_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 34cf20de..714ceb16 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1302,10 +1302,6 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { return 0x00000004; } -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028; -} static inline u32 gr_ds_zbc_z_r(void) { return 0x00405818; diff --git a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h index 96e21899..3750de06 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, -- cgit v1.2.2