From e9de95d7e0629c40b5ceb56c07de319bedd3339f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 9 Jan 2018 14:33:51 -0800 Subject: gpu: nvgpu: use chip specific zbc_c/z format reg Use chip specific gpcs_swdx_dss_zbc_c_format_reg and gpcs_swdx_dss_zbc_z_format_reg. These registers are different for gv11b/gv100 from gp10b/gp106. Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1635091 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 +++- drivers/gpu/nvgpu/gp106/hal_gp106.c | 6 +++++- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 22 ++++++++++++++++++---- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 4 +++- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 +++++- drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 +++++- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 10 ++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ 9 files changed, 55 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d9a8396f..a1c9c2bd 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * GK20A Graphics * @@ -437,6 +437,8 @@ struct gpu_ops { unsigned long (*get_max_gfxp_wfi_timeout_count) (struct gk20a *g); void (*ecc_init_scrub_reg)(struct gk20a *g); + u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g); + u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 9052b4b2..dc3b7868 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -1,7 +1,7 @@ /* * GP106 HAL interface * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -281,6 +281,10 @@ static const struct gpu_ops gp106_ops = { .detect_sm_arch = gr_gm20b_detect_sm_arch, .add_zbc_color = gr_gp10b_add_zbc_color, .add_zbc_depth = gr_gp10b_add_zbc_depth, + .get_gpcs_swdx_dss_zbc_c_format_reg = + gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg, + .get_gpcs_swdx_dss_zbc_z_format_reg = + gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg, .zbc_set_table = gk20a_gr_zbc_set_table, .zbc_query_table = gr_gk20a_query_zbc, .pmu_save_zbc = gk20a_pmu_save_zbc, diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a7f4f97..68d18aa1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -507,11 +507,18 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, gr_gpcs_gcc_pagepool_total_pages_f(size), patch); } +u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g) +{ + return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(); +} + int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index) { u32 i; u32 zbc_c; + u32 zbc_c_format_reg = + g->ops.gr.get_gpcs_swdx_dss_zbc_c_format_reg(g); /* update l2 table */ g->ops.ltc.set_zbc_color_entry(g, color_val, index); @@ -554,18 +561,25 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, color_val->color_ds[2]); gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); - zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); + zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); zbc_c &= ~(0x7f << ((index % 4) * 7)); zbc_c |= color_val->format << ((index % 4) * 7); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); + gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c); return 0; } +u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) +{ + return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); +} + int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index) { u32 zbc_z; + u32 zbc_z_format_reg = + g->ops.gr.get_gpcs_swdx_dss_zbc_z_format_reg(g); /* update l2 table */ g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); @@ -592,10 +606,10 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, gr->zbc_dep_tbl[index].ref_cnt++; gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); - zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); + zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3)); zbc_z &= ~(0x7f << (index % 4) * 7); zbc_z |= depth_val->format << (index % 4) * 7; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); + gk20a_writel(g, zbc_z_format_reg + (index & ~3), zbc_z); return 0; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 3b0f0f2e..1d39a38b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -1,7 +1,7 @@ /* * GP10B GPU GR * - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -77,6 +77,8 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, void gr_gp10b_commit_global_pagepool(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, u32 size, bool patch); +u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g); +u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g); int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index); int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 5e8e7acc..cfba7d65 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -245,6 +245,10 @@ static const struct gpu_ops gp10b_ops = { .detect_sm_arch = gr_gm20b_detect_sm_arch, .add_zbc_color = gr_gp10b_add_zbc_color, .add_zbc_depth = gr_gp10b_add_zbc_depth, + .get_gpcs_swdx_dss_zbc_c_format_reg = + gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg, + .get_gpcs_swdx_dss_zbc_z_format_reg = + gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg, .zbc_set_table = gk20a_gr_zbc_set_table, .zbc_query_table = gr_gk20a_query_zbc, .pmu_save_zbc = gk20a_pmu_save_zbc, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9c847a55..e935b2e5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -1,7 +1,7 @@ /* * GV100 Tegra HAL interface * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -314,6 +314,10 @@ static const struct gpu_ops gv100_ops = { .detect_sm_arch = gr_gv11b_detect_sm_arch, .add_zbc_color = gr_gp10b_add_zbc_color, .add_zbc_depth = gr_gp10b_add_zbc_depth, + .get_gpcs_swdx_dss_zbc_c_format_reg = + gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg, + .get_gpcs_swdx_dss_zbc_z_format_reg = + gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg, .zbc_set_table = gk20a_gr_zbc_set_table, .zbc_query_table = gr_gk20a_query_zbc, .pmu_save_zbc = gk20a_pmu_save_zbc, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f369e12e..baad5e47 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -4152,3 +4152,13 @@ void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); } + +u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g) +{ + return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(); +} + +u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) +{ + return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); +} diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 17e5e9e3..b69e69bd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -102,6 +102,8 @@ int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, u32 gpc_exception); void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); +u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g); +u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g); int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, bool *post_event); int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9156d9b8..f19832b9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -281,6 +281,10 @@ static const struct gpu_ops gv11b_ops = { .detect_sm_arch = gr_gv11b_detect_sm_arch, .add_zbc_color = gr_gp10b_add_zbc_color, .add_zbc_depth = gr_gp10b_add_zbc_depth, + .get_gpcs_swdx_dss_zbc_c_format_reg = + gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg, + .get_gpcs_swdx_dss_zbc_z_format_reg = + gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg, .zbc_set_table = gk20a_gr_zbc_set_table, .zbc_query_table = gr_gk20a_query_zbc, .pmu_save_zbc = gk20a_pmu_save_zbc, -- cgit v1.2.2