From e7a0c0ae8b6791c6b8ee30270ebdbe6e95fbbc71 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 19:18:21 -0800 Subject: gpu: nvgpu: Move from gk20a_ to nvgpu_ in semaphore code Change the prefix in the semaphore code to 'nvgpu_' since this code is global to all chips. Bug 1799159 Change-Id: Ic1f3e13428882019e5d1f547acfe95271cc10da5 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284628 Reviewed-by: Varun Colbert Tested-by: Varun Colbert --- drivers/gpu/nvgpu/common/semaphore.c | 72 +++++++++++------------ drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 6 +- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c | 58 +++++++++---------- drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h | 1 - drivers/gpu/nvgpu/gk20a/debug_gk20a.c | 4 +- drivers/gpu/nvgpu/gk20a/fence_gk20a.c | 26 ++++----- drivers/gpu/nvgpu/gk20a/fence_gk20a.h | 6 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 14 ++--- drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/sync_gk20a.c | 26 ++++----- drivers/gpu/nvgpu/gk20a/sync_gk20a.h | 6 +- drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 86 ++++++++++++++-------------- 14 files changed, 155 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/nvgpu/common/semaphore.c b/drivers/gpu/nvgpu/common/semaphore.c index ea4910f1..4bf8695d 100644 --- a/drivers/gpu/nvgpu/common/semaphore.c +++ b/drivers/gpu/nvgpu/common/semaphore.c @@ -37,12 +37,12 @@ /* * Return the sema_sea pointer. */ -struct gk20a_semaphore_sea *gk20a_semaphore_get_sea(struct gk20a *g) +struct nvgpu_semaphore_sea *nvgpu_semaphore_get_sea(struct gk20a *g) { return g->sema_sea; } -static int __gk20a_semaphore_sea_grow(struct gk20a_semaphore_sea *sea) +static int __nvgpu_semaphore_sea_grow(struct nvgpu_semaphore_sea *sea) { int ret = 0; struct gk20a *gk20a = sea->gk20a; @@ -68,7 +68,7 @@ out: * Create the semaphore sea. Only create it once - subsequent calls to this will * return the originally created sea pointer. */ -struct gk20a_semaphore_sea *gk20a_semaphore_sea_create(struct gk20a *g) +struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *g) { if (g->sema_sea) return g->sema_sea; @@ -83,7 +83,7 @@ struct gk20a_semaphore_sea *gk20a_semaphore_sea_create(struct gk20a *g) INIT_LIST_HEAD(&g->sema_sea->pool_list); mutex_init(&g->sema_sea->sea_lock); - if (__gk20a_semaphore_sea_grow(g->sema_sea)) + if (__nvgpu_semaphore_sea_grow(g->sema_sea)) goto cleanup; gpu_sema_dbg("Created semaphore sea!"); @@ -111,10 +111,10 @@ static int __semaphore_bitmap_alloc(unsigned long *bitmap, unsigned long len) /* * Allocate a pool from the sea. */ -struct gk20a_semaphore_pool *gk20a_semaphore_pool_alloc( - struct gk20a_semaphore_sea *sea) +struct nvgpu_semaphore_pool *nvgpu_semaphore_pool_alloc( + struct nvgpu_semaphore_sea *sea) { - struct gk20a_semaphore_pool *p; + struct nvgpu_semaphore_pool *p; unsigned long page_idx; int ret, err = 0; @@ -159,7 +159,7 @@ fail: * Map a pool into the passed vm's address space. This handles both the fixed * global RO mapping and the non-fixed private RW mapping. */ -int gk20a_semaphore_pool_map(struct gk20a_semaphore_pool *p, +int nvgpu_semaphore_pool_map(struct nvgpu_semaphore_pool *p, struct vm_gk20a *vm) { int ents, err = 0; @@ -252,10 +252,10 @@ fail: /* * Unmap a semaphore_pool. */ -void gk20a_semaphore_pool_unmap(struct gk20a_semaphore_pool *p, +void nvgpu_semaphore_pool_unmap(struct nvgpu_semaphore_pool *p, struct vm_gk20a *vm) { - struct gk20a_semaphore_int *hw_sema; + struct nvgpu_semaphore_int *hw_sema; kunmap(p->cpu_va); @@ -291,12 +291,12 @@ void gk20a_semaphore_pool_unmap(struct gk20a_semaphore_pool *p, * Completely free a sempahore_pool. You should make sure this pool is not * mapped otherwise there's going to be a memory leak. */ -static void gk20a_semaphore_pool_free(struct kref *ref) +static void nvgpu_semaphore_pool_free(struct kref *ref) { - struct gk20a_semaphore_pool *p = - container_of(ref, struct gk20a_semaphore_pool, ref); - struct gk20a_semaphore_sea *s = p->sema_sea; - struct gk20a_semaphore_int *hw_sema, *tmp; + struct nvgpu_semaphore_pool *p = + container_of(ref, struct nvgpu_semaphore_pool, ref); + struct nvgpu_semaphore_sea *s = p->sema_sea; + struct nvgpu_semaphore_int *hw_sema, *tmp; WARN_ON(p->gpu_va || p->rw_sg_table || p->ro_sg_table); @@ -313,21 +313,21 @@ static void gk20a_semaphore_pool_free(struct kref *ref) kfree(p); } -void gk20a_semaphore_pool_get(struct gk20a_semaphore_pool *p) +void nvgpu_semaphore_pool_get(struct nvgpu_semaphore_pool *p) { kref_get(&p->ref); } -void gk20a_semaphore_pool_put(struct gk20a_semaphore_pool *p) +void nvgpu_semaphore_pool_put(struct nvgpu_semaphore_pool *p) { - kref_put(&p->ref, gk20a_semaphore_pool_free); + kref_put(&p->ref, nvgpu_semaphore_pool_free); } /* * Get the address for a semaphore_pool - if global is true then return the * global RO address instead of the RW address owned by the semaphore's VM. */ -u64 __gk20a_semaphore_pool_gpu_va(struct gk20a_semaphore_pool *p, bool global) +u64 __nvgpu_semaphore_pool_gpu_va(struct nvgpu_semaphore_pool *p, bool global) { if (!global) return p->gpu_va; @@ -335,12 +335,12 @@ u64 __gk20a_semaphore_pool_gpu_va(struct gk20a_semaphore_pool *p, bool global) return p->gpu_va_ro + (PAGE_SIZE * p->page_idx); } -static int __gk20a_init_hw_sema(struct channel_gk20a *ch) +static int __nvgpu_init_hw_sema(struct channel_gk20a *ch) { int hw_sema_idx; int ret = 0; - struct gk20a_semaphore_int *hw_sema; - struct gk20a_semaphore_pool *p = ch->vm->sema_pool; + struct nvgpu_semaphore_int *hw_sema; + struct nvgpu_semaphore_pool *p = ch->vm->sema_pool; BUG_ON(!p); @@ -354,7 +354,7 @@ static int __gk20a_init_hw_sema(struct channel_gk20a *ch) goto fail; } - hw_sema = kzalloc(sizeof(struct gk20a_semaphore_int), GFP_KERNEL); + hw_sema = kzalloc(sizeof(struct nvgpu_semaphore_int), GFP_KERNEL); if (!hw_sema) { ret = -ENOMEM; goto fail_free_idx; @@ -385,9 +385,9 @@ fail: /* * Free the channel used semaphore index */ -void gk20a_semaphore_free_hw_sema(struct channel_gk20a *ch) +void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch) { - struct gk20a_semaphore_pool *p = ch->vm->sema_pool; + struct nvgpu_semaphore_pool *p = ch->vm->sema_pool; BUG_ON(!p); @@ -409,13 +409,13 @@ void gk20a_semaphore_free_hw_sema(struct channel_gk20a *ch) * Since semaphores are ref-counted there's no explicit free for external code * to use. When the ref-count hits 0 the internal free will happen. */ -struct gk20a_semaphore *gk20a_semaphore_alloc(struct channel_gk20a *ch) +struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch) { - struct gk20a_semaphore *s; + struct nvgpu_semaphore *s; int ret; if (!ch->hw_sema) { - ret = __gk20a_init_hw_sema(ch); + ret = __nvgpu_init_hw_sema(ch); if (ret) return NULL; } @@ -432,29 +432,29 @@ struct gk20a_semaphore *gk20a_semaphore_alloc(struct channel_gk20a *ch) * Take a ref on the pool so that we can keep this pool alive for * as long as this semaphore is alive. */ - gk20a_semaphore_pool_get(s->hw_sema->p); + nvgpu_semaphore_pool_get(s->hw_sema->p); gpu_sema_dbg("Allocated semaphore (c=%d)", ch->hw_chid); return s; } -static void gk20a_semaphore_free(struct kref *ref) +static void nvgpu_semaphore_free(struct kref *ref) { - struct gk20a_semaphore *s = - container_of(ref, struct gk20a_semaphore, ref); + struct nvgpu_semaphore *s = + container_of(ref, struct nvgpu_semaphore, ref); - gk20a_semaphore_pool_put(s->hw_sema->p); + nvgpu_semaphore_pool_put(s->hw_sema->p); kfree(s); } -void gk20a_semaphore_put(struct gk20a_semaphore *s) +void nvgpu_semaphore_put(struct nvgpu_semaphore *s) { - kref_put(&s->ref, gk20a_semaphore_free); + kref_put(&s->ref, nvgpu_semaphore_free); } -void gk20a_semaphore_get(struct gk20a_semaphore *s) +void nvgpu_semaphore_get(struct nvgpu_semaphore *s) { kref_get(&s->ref); } diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 3fa6bb25..b963ad96 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -515,7 +515,7 @@ void gk20a_channel_abort_clean_up(struct channel_gk20a *ch) while (tmp_get != put) { job = &ch->joblist.pre_alloc.jobs[tmp_get]; if (job->post_fence->semaphore) { - __gk20a_semaphore_release( + __nvgpu_semaphore_release( job->post_fence->semaphore, true); released_job_semaphore = true; } @@ -525,7 +525,7 @@ void gk20a_channel_abort_clean_up(struct channel_gk20a *ch) list_for_each_entry_safe(job, n, &ch->joblist.dynamic.jobs, list) { if (job->post_fence->semaphore) { - __gk20a_semaphore_release( + __nvgpu_semaphore_release( job->post_fence->semaphore, true); released_job_semaphore = true; } @@ -1006,7 +1006,7 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force) * as the semaphore pool might get freed after that point. */ if (ch->hw_sema) - gk20a_semaphore_free_hw_sema(ch); + nvgpu_semaphore_free_hw_sema(ch); /* * When releasing the channel we unbind the VM - so release the ref. diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index fce3f461..f940a271 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -172,7 +172,7 @@ struct channel_gk20a { spinlock_t ref_actions_lock; #endif - struct gk20a_semaphore_int *hw_sema; + struct nvgpu_semaphore_int *hw_sema; int hw_chid; bool wdt_enabled; diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c index 0eba1c30..18971b09 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c @@ -388,7 +388,7 @@ struct gk20a_channel_semaphore { struct channel_gk20a *c; /* A semaphore pool owned by this channel. */ - struct gk20a_semaphore_pool *pool; + struct nvgpu_semaphore_pool *pool; /* A sync timeline that advances when gpu completes work. */ struct sync_timeline *timeline; @@ -399,7 +399,7 @@ struct wait_fence_work { struct sync_fence_waiter waiter; struct sync_fence *fence; struct channel_gk20a *ch; - struct gk20a_semaphore *sema; + struct nvgpu_semaphore *sema; struct gk20a *g; struct list_head entry; }; @@ -501,14 +501,14 @@ static void gk20a_channel_semaphore_launcher( "wait completed (%d) for fence %p '%s', triggering gpu work", err, fence, fence->name); sync_fence_put(fence); - gk20a_semaphore_release(w->sema); - gk20a_semaphore_put(w->sema); + nvgpu_semaphore_release(w->sema); + nvgpu_semaphore_put(w->sema); kfree(w); } #endif static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, - struct gk20a_semaphore *s, struct priv_cmd_entry *cmd, + struct nvgpu_semaphore *s, struct priv_cmd_entry *cmd, int cmd_size, bool acquire, bool wfi) { int ch = c->hw_chid; @@ -521,15 +521,15 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, * RO for acquire (since we just need to read the mem) and RW for * release since we will need to write back to the semaphore memory. */ - va = acquire ? gk20a_semaphore_gpu_ro_va(s) : - gk20a_semaphore_gpu_rw_va(s); + va = acquire ? nvgpu_semaphore_gpu_ro_va(s) : + nvgpu_semaphore_gpu_rw_va(s); /* * If the op is not an acquire (so therefor a release) we should * incr the underlying sema next_value. */ if (!acquire) - gk20a_semaphore_incr(s); + nvgpu_semaphore_incr(s); /* semaphore_a */ gk20a_mem_wr32(g, cmd->mem, off++, 0x20010004); @@ -545,7 +545,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, gk20a_mem_wr32(g, cmd->mem, off++, 0x20010006); /* payload */ gk20a_mem_wr32(g, cmd->mem, off++, - gk20a_semaphore_get_value(s)); + nvgpu_semaphore_get_value(s)); /* semaphore_d */ gk20a_mem_wr32(g, cmd->mem, off++, 0x20010007); /* operation: acq_geq, switch_en */ @@ -555,7 +555,7 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, gk20a_mem_wr32(g, cmd->mem, off++, 0x20010006); /* payload */ gk20a_mem_wr32(g, cmd->mem, off++, - gk20a_semaphore_get_value(s)); + nvgpu_semaphore_get_value(s)); /* semaphore_d */ gk20a_mem_wr32(g, cmd->mem, off++, 0x20010007); /* operation: release, wfi */ @@ -570,13 +570,13 @@ static void add_sema_cmd(struct gk20a *g, struct channel_gk20a *c, if (acquire) gpu_sema_verbose_dbg("(A) c=%d ACQ_GE %-4u owner=%-3d" "va=0x%llx cmd_mem=0x%llx b=0x%llx off=%u", - ch, gk20a_semaphore_get_value(s), + ch, nvgpu_semaphore_get_value(s), s->hw_sema->ch->hw_chid, va, cmd->gva, cmd->mem->gpu_va, ob); else gpu_sema_verbose_dbg("(R) c=%d INCR %u (%u) va=0x%llx " "cmd_mem=0x%llx b=0x%llx off=%u", - ch, gk20a_semaphore_get_value(s), + ch, nvgpu_semaphore_get_value(s), readl(s->hw_sema->value), va, cmd->gva, cmd->mem->gpu_va, ob); } @@ -596,7 +596,7 @@ static int gk20a_channel_semaphore_wait_syncpt( #ifdef CONFIG_SYNC /* * Attempt a fast path for waiting on a sync_fence. Basically if the passed - * sync_fence is backed by a gk20a_semaphore then there's no reason to go + * sync_fence is backed by a nvgpu_semaphore then there's no reason to go * through the rigmarole of setting up a separate semaphore which waits on an * interrupt from the GPU and then triggers a worker thread to execute a SW * based semaphore release. Instead just have the GPU wait on the same semaphore @@ -609,9 +609,9 @@ static int gk20a_channel_semaphore_wait_syncpt( static int __semaphore_wait_fd_fast_path(struct channel_gk20a *c, struct sync_fence *fence, struct priv_cmd_entry *wait_cmd, - struct gk20a_semaphore **fp_sema) + struct nvgpu_semaphore **fp_sema) { - struct gk20a_semaphore *sema; + struct nvgpu_semaphore *sema; int err; if (!gk20a_is_sema_backed_sync_fence(fence)) @@ -632,7 +632,7 @@ static int __semaphore_wait_fd_fast_path(struct channel_gk20a *c, if (err) return err; - gk20a_semaphore_get(sema); + nvgpu_semaphore_get(sema); BUG_ON(!atomic_read(&sema->value)); add_sema_cmd(c->g, c, sema, wait_cmd, 8, true, false); @@ -655,7 +655,7 @@ static int gk20a_channel_semaphore_wait_fd( container_of(s, struct gk20a_channel_semaphore, ops); struct channel_gk20a *c = sema->c; #ifdef CONFIG_SYNC - struct gk20a_semaphore *fp_sema; + struct nvgpu_semaphore *fp_sema; struct sync_fence *sync_fence; struct priv_cmd_entry *wait_cmd = entry; struct wait_fence_work *w = NULL; @@ -674,7 +674,7 @@ static int gk20a_channel_semaphore_wait_fd( &c->semaphore_wq, NULL, false, false); if (err) { - gk20a_semaphore_put(fp_sema); + nvgpu_semaphore_put(fp_sema); goto clean_up_priv_cmd; } } else @@ -716,7 +716,7 @@ static int gk20a_channel_semaphore_wait_fd( w->fence = sync_fence; w->g = c->g; w->ch = c; - w->sema = gk20a_semaphore_alloc(c); + w->sema = nvgpu_semaphore_alloc(c); if (!w->sema) { gk20a_err(dev_from_gk20a(c->g), "ran out of semaphores"); err = -ENOMEM; @@ -724,8 +724,8 @@ static int gk20a_channel_semaphore_wait_fd( } /* worker takes one reference */ - gk20a_semaphore_get(w->sema); - gk20a_semaphore_incr(w->sema); + nvgpu_semaphore_get(w->sema); + nvgpu_semaphore_incr(w->sema); /* GPU unblocked when the semaphore value increments. */ add_sema_cmd(c->g, c, w->sema, wait_cmd, 8, true, false); @@ -747,12 +747,12 @@ static int gk20a_channel_semaphore_wait_fd( * If the sync_fence has already signaled then the above async_wait * will never trigger. This causes the semaphore release op to never * happen which, in turn, hangs the GPU. That's bad. So let's just - * do the gk20a_semaphore_release() right now. + * do the nvgpu_semaphore_release() right now. */ if (ret == 1) { sync_fence_put(sync_fence); - gk20a_semaphore_release(w->sema); - gk20a_semaphore_put(w->sema); + nvgpu_semaphore_release(w->sema); + nvgpu_semaphore_put(w->sema); } skip_slow_path: @@ -763,8 +763,8 @@ clean_up_sema: * Release the refs to the semaphore, including * the one for the worker since it will never run. */ - gk20a_semaphore_put(w->sema); - gk20a_semaphore_put(w->sema); + nvgpu_semaphore_put(w->sema); + nvgpu_semaphore_put(w->sema); clean_up_worker: kfree(w); clean_up_priv_cmd: @@ -790,10 +790,10 @@ static int __gk20a_channel_semaphore_incr( struct gk20a_channel_semaphore *sp = container_of(s, struct gk20a_channel_semaphore, ops); struct channel_gk20a *c = sp->c; - struct gk20a_semaphore *semaphore; + struct nvgpu_semaphore *semaphore; int err = 0; - semaphore = gk20a_semaphore_alloc(c); + semaphore = nvgpu_semaphore_alloc(c); if (!semaphore) { gk20a_err(dev_from_gk20a(c->g), "ran out of semaphores"); @@ -824,7 +824,7 @@ static int __gk20a_channel_semaphore_incr( clean_up_priv_cmd: gk20a_free_priv_cmdbuf(c, incr_cmd); clean_up_sema: - gk20a_semaphore_put(semaphore); + nvgpu_semaphore_put(semaphore); return err; } diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h index d9ad12ad..c3136023 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.h @@ -23,7 +23,6 @@ struct gk20a_channel_sync; struct priv_cmd_entry; struct channel_gk20a; -struct gk20a_semaphore; struct gk20a_fence; struct gk20a; diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c index 83fdc05d..d20229b3 100644 --- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c @@ -109,7 +109,7 @@ static void gk20a_debug_show_channel(struct gk20a *g, u32 syncpointa, syncpointb; u32 *inst_mem; struct channel_gk20a *c = g->fifo.channel + hw_chid; - struct gk20a_semaphore_int *hw_sema = NULL; + struct nvgpu_semaphore_int *hw_sema = NULL; if (c->hw_sema) hw_sema = c->hw_sema; @@ -154,7 +154,7 @@ static void gk20a_debug_show_channel(struct gk20a *g, "next_val: 0x%08x addr: 0x%010llx\n", readl(hw_sema->value), atomic_read(&hw_sema->next_value), - gk20a_hw_sema_addr(hw_sema)); + nvgpu_hw_sema_addr(hw_sema)); #ifdef CONFIG_TEGRA_GK20A if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v()) diff --git a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c index 6bd59067..115cd2b5 100644 --- a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c @@ -47,7 +47,7 @@ static void gk20a_fence_free(struct kref *ref) sync_fence_put(f->sync_fence); #endif if (f->semaphore) - gk20a_semaphore_put(f->semaphore); + nvgpu_semaphore_put(f->semaphore); if (f->allocator) { if (nvgpu_alloc_initialized(f->allocator)) @@ -193,39 +193,39 @@ void gk20a_init_fence(struct gk20a_fence *f, /* Fences that are backed by GPU semaphores: */ -static int gk20a_semaphore_fence_wait(struct gk20a_fence *f, long timeout) +static int nvgpu_semaphore_fence_wait(struct gk20a_fence *f, long timeout) { long remain; - if (!gk20a_semaphore_is_acquired(f->semaphore)) + if (!nvgpu_semaphore_is_acquired(f->semaphore)) return 0; remain = wait_event_interruptible_timeout( *f->semaphore_wq, - !gk20a_semaphore_is_acquired(f->semaphore), + !nvgpu_semaphore_is_acquired(f->semaphore), timeout); - if (remain == 0 && gk20a_semaphore_is_acquired(f->semaphore)) + if (remain == 0 && nvgpu_semaphore_is_acquired(f->semaphore)) return -ETIMEDOUT; else if (remain < 0) return remain; return 0; } -static bool gk20a_semaphore_fence_is_expired(struct gk20a_fence *f) +static bool nvgpu_semaphore_fence_is_expired(struct gk20a_fence *f) { - return !gk20a_semaphore_is_acquired(f->semaphore); + return !nvgpu_semaphore_is_acquired(f->semaphore); } -static const struct gk20a_fence_ops gk20a_semaphore_fence_ops = { - .wait = &gk20a_semaphore_fence_wait, - .is_expired = &gk20a_semaphore_fence_is_expired, +static const struct gk20a_fence_ops nvgpu_semaphore_fence_ops = { + .wait = &nvgpu_semaphore_fence_wait, + .is_expired = &nvgpu_semaphore_fence_is_expired, }; /* This function takes ownership of the semaphore */ int gk20a_fence_from_semaphore( struct gk20a_fence *fence_out, struct sync_timeline *timeline, - struct gk20a_semaphore *semaphore, + struct nvgpu_semaphore *semaphore, wait_queue_head_t *semaphore_wq, struct sync_fence *dependency, bool wfi, bool need_sync_fence) @@ -237,13 +237,13 @@ int gk20a_fence_from_semaphore( if (need_sync_fence) { sync_fence = gk20a_sync_fence_create(timeline, semaphore, dependency, "f-gk20a-0x%04x", - gk20a_semaphore_gpu_ro_va(semaphore)); + nvgpu_semaphore_gpu_ro_va(semaphore)); if (!sync_fence) return -1; } #endif - gk20a_init_fence(f, &gk20a_semaphore_fence_ops, sync_fence, wfi); + gk20a_init_fence(f, &nvgpu_semaphore_fence_ops, sync_fence, wfi); if (!f) { #ifdef CONFIG_SYNC if (sync_fence) diff --git a/drivers/gpu/nvgpu/gk20a/fence_gk20a.h b/drivers/gpu/nvgpu/gk20a/fence_gk20a.h index 5abf96e5..b4283f58 100644 --- a/drivers/gpu/nvgpu/gk20a/fence_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fence_gk20a.h @@ -24,7 +24,7 @@ struct platform_device; struct sync_timeline; struct sync_fence; -struct gk20a_semaphore; +struct nvgpu_semaphore; struct channel_gk20a; struct gk20a_fence_ops; @@ -38,7 +38,7 @@ struct gk20a_fence { const struct gk20a_fence_ops *ops; /* Valid for fences created from semaphores: */ - struct gk20a_semaphore *semaphore; + struct nvgpu_semaphore *semaphore; wait_queue_head_t *semaphore_wq; /* Valid for fences created from syncpoints: */ @@ -54,7 +54,7 @@ struct gk20a_fence { int gk20a_fence_from_semaphore( struct gk20a_fence *fence_out, struct sync_timeline *timeline, - struct gk20a_semaphore *semaphore, + struct nvgpu_semaphore *semaphore, wait_queue_head_t *semaphore_wq, struct sync_fence *dependency, bool wfi, bool need_sync_fence); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 39be4e9c..8d6d36fc 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -922,7 +922,7 @@ struct gk20a { /* * A group of semaphore pools. One for each channel. */ - struct gk20a_semaphore_sea *sema_sea; + struct nvgpu_semaphore_sea *sema_sea; /* List of pending SW semaphore waits. */ struct list_head pending_sema_waits; diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index cafb1233..c62d1f6c 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -4096,8 +4096,8 @@ static void gk20a_vm_remove_support_nofree(struct vm_gk20a *vm) */ if (!gk20a_platform_has_syncpoints(gk20a_from_vm(vm)->dev)) { if (vm->sema_pool) { - gk20a_semaphore_pool_unmap(vm->sema_pool, vm); - gk20a_semaphore_pool_put(vm->sema_pool); + nvgpu_semaphore_pool_unmap(vm->sema_pool, vm); + nvgpu_semaphore_pool_put(vm->sema_pool); } } @@ -4180,7 +4180,7 @@ const struct gk20a_mmu_level gk20a_mm_levels_128k[] = { */ static int gk20a_init_sema_pool(struct vm_gk20a *vm) { - struct gk20a_semaphore_sea *sema_sea; + struct nvgpu_semaphore_sea *sema_sea; struct mm_gk20a *mm = vm->mm; struct gk20a *g = mm->g; int err; @@ -4194,11 +4194,11 @@ static int gk20a_init_sema_pool(struct vm_gk20a *vm) if (vm->sema_pool) return 0; - sema_sea = gk20a_semaphore_sea_create(g); + sema_sea = nvgpu_semaphore_sea_create(g); if (!sema_sea) return -ENOMEM; - vm->sema_pool = gk20a_semaphore_pool_alloc(sema_sea); + vm->sema_pool = nvgpu_semaphore_pool_alloc(sema_sea); if (!vm->sema_pool) return -ENOMEM; @@ -4220,9 +4220,9 @@ static int gk20a_init_sema_pool(struct vm_gk20a *vm) return -ENOMEM; } - err = gk20a_semaphore_pool_map(vm->sema_pool, vm); + err = nvgpu_semaphore_pool_map(vm->sema_pool, vm); if (err) { - gk20a_semaphore_pool_unmap(vm->sema_pool, vm); + nvgpu_semaphore_pool_unmap(vm->sema_pool, vm); nvgpu_free(vm->vma[gmmu_page_size_small], vm->sema_pool->gpu_va); return err; diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index d39ca2d0..294dc628 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h @@ -303,7 +303,7 @@ struct vm_gk20a { /* * Each address space needs to have a semaphore pool. */ - struct gk20a_semaphore_pool *sema_pool; + struct nvgpu_semaphore_pool *sema_pool; }; struct gk20a; diff --git a/drivers/gpu/nvgpu/gk20a/sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/sync_gk20a.c index e7bacac8..edfe3deb 100644 --- a/drivers/gpu/nvgpu/gk20a/sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/sync_gk20a.c @@ -45,7 +45,7 @@ struct gk20a_sync_timeline { struct gk20a_sync_pt { struct kref refcount; u32 thresh; - struct gk20a_semaphore *sema; + struct nvgpu_semaphore *sema; struct gk20a_sync_timeline *obj; struct sync_fence *dep; ktime_t dep_timestamp; @@ -110,7 +110,7 @@ int gk20a_is_sema_backed_sync_fence(struct sync_fence *fence) return 0; } -struct gk20a_semaphore *gk20a_sync_fence_get_sema(struct sync_fence *f) +struct nvgpu_semaphore *gk20a_sync_fence_get_sema(struct sync_fence *f) { struct sync_pt *spt; struct gk20a_sync_pt_inst *pti; @@ -208,13 +208,13 @@ static void gk20a_sync_pt_free_shared(struct kref *ref) if (pt->dep) sync_fence_put(pt->dep); if (pt->sema) - gk20a_semaphore_put(pt->sema); + nvgpu_semaphore_put(pt->sema); kfree(pt); } static struct gk20a_sync_pt *gk20a_sync_pt_create_shared( struct gk20a_sync_timeline *obj, - struct gk20a_semaphore *sema, + struct nvgpu_semaphore *sema, struct sync_fence *dependency) { struct gk20a_sync_pt *shared; @@ -244,14 +244,14 @@ static struct gk20a_sync_pt *gk20a_sync_pt_create_shared( spin_lock_init(&shared->lock); - gk20a_semaphore_get(sema); + nvgpu_semaphore_get(sema); return shared; } static struct sync_pt *gk20a_sync_pt_create_inst( struct gk20a_sync_timeline *obj, - struct gk20a_semaphore *sema, + struct nvgpu_semaphore *sema, struct sync_fence *dependency) { struct gk20a_sync_pt_inst *pti; @@ -309,7 +309,7 @@ static int gk20a_sync_pt_has_signaled(struct sync_pt *sync_pt) goto done; /* Acquired == not realeased yet == active == not signaled. */ - signaled = !gk20a_semaphore_is_acquired(pt->sema); + signaled = !nvgpu_semaphore_is_acquired(pt->sema); if (signaled) { /* Update min if necessary. */ @@ -341,7 +341,7 @@ static int gk20a_sync_pt_has_signaled(struct sync_pt *sync_pt) } /* Release the semaphore to the pool. */ - gk20a_semaphore_put(pt->sema); + nvgpu_semaphore_put(pt->sema); pt->sema = NULL; } done: @@ -410,12 +410,12 @@ static void gk20a_sync_timeline_value_str(struct sync_timeline *timeline, static void gk20a_sync_pt_value_str_for_sema(struct gk20a_sync_pt *pt, char *str, int size) { - struct gk20a_semaphore *s = pt->sema; + struct nvgpu_semaphore *s = pt->sema; snprintf(str, size, "S: c=%d [v=%u,r_v=%u]", s->hw_sema->ch->hw_chid, - gk20a_semaphore_get_value(s), - gk20a_semaphore_read(s)); + nvgpu_semaphore_get_value(s), + nvgpu_semaphore_read(s)); } static void gk20a_sync_pt_value_str(struct sync_pt *sync_pt, char *str, @@ -458,7 +458,7 @@ static int gk20a_sync_fill_driver_data(struct sync_pt *sync_pt, } static const struct sync_timeline_ops gk20a_sync_timeline_ops = { - .driver_name = "gk20a_semaphore", + .driver_name = "nvgpu_semaphore", .dup = gk20a_sync_pt_dup_inst, .has_signaled = gk20a_sync_pt_has_signaled, .compare = gk20a_sync_pt_compare, @@ -508,7 +508,7 @@ struct sync_timeline *gk20a_sync_timeline_create( } struct sync_fence *gk20a_sync_fence_create(struct sync_timeline *obj, - struct gk20a_semaphore *sema, + struct nvgpu_semaphore *sema, struct sync_fence *dependency, const char *fmt, ...) { diff --git a/drivers/gpu/nvgpu/gk20a/sync_gk20a.h b/drivers/gpu/nvgpu/gk20a/sync_gk20a.h index 88bf07cd..dcced5c8 100644 --- a/drivers/gpu/nvgpu/gk20a/sync_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/sync_gk20a.h @@ -24,18 +24,18 @@ struct sync_timeline; struct sync_fence; struct sync_pt; -struct gk20a_semaphore; +struct nvgpu_semaphore; struct fence; int gk20a_is_sema_backed_sync_fence(struct sync_fence *fence); -struct gk20a_semaphore *gk20a_sync_fence_get_sema(struct sync_fence *f); +struct nvgpu_semaphore *gk20a_sync_fence_get_sema(struct sync_fence *f); #ifdef CONFIG_SYNC struct sync_timeline *gk20a_sync_timeline_create(const char *fmt, ...); void gk20a_sync_timeline_destroy(struct sync_timeline *); void gk20a_sync_timeline_signal(struct sync_timeline *); struct sync_fence *gk20a_sync_fence_create(struct sync_timeline *, - struct gk20a_semaphore *, + struct nvgpu_semaphore *, struct sync_fence *dependency, const char *fmt, ...); struct sync_fence *gk20a_sync_fence_fdget(int fd); diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index 07a27584..cc4921d3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h @@ -37,19 +37,19 @@ #define SEMAPHORE_SIZE 16 #define SEMAPHORE_SEA_GROWTH_RATE 32 -struct gk20a_semaphore_sea; +struct nvgpu_semaphore_sea; /* * Underlying semaphore data structure. This semaphore can be shared amongst * other semaphore instances. */ -struct gk20a_semaphore_int { +struct nvgpu_semaphore_int { int idx; /* Semaphore index. */ u32 offset; /* Offset into the pool. */ atomic_t next_value; /* Next available value. */ u32 *value; /* Current value (access w/ readl()). */ u32 nr_incrs; /* Number of increments programmed. */ - struct gk20a_semaphore_pool *p; /* Pool that owns this sema. */ + struct nvgpu_semaphore_pool *p; /* Pool that owns this sema. */ struct channel_gk20a *ch; /* Channel that owns this sema. */ struct list_head hw_sema_list; /* List of HW semaphores. */ }; @@ -59,8 +59,8 @@ struct gk20a_semaphore_int { * pointer to a real semaphore and a value to wait for. This allows one physical * semaphore to be shared among an essentially infinite number of submits. */ -struct gk20a_semaphore { - struct gk20a_semaphore_int *hw_sema; +struct nvgpu_semaphore { + struct nvgpu_semaphore_int *hw_sema; atomic_t value; int incremented; @@ -71,7 +71,7 @@ struct gk20a_semaphore { /* * A semaphore pool. Each address space will own exactly one of these. */ -struct gk20a_semaphore_pool { +struct nvgpu_semaphore_pool { struct page *page; /* This pool's page of memory */ struct list_head pool_list_entry; /* Node for list of pools. */ void *cpu_va; /* CPU access to the pool. */ @@ -82,7 +82,7 @@ struct gk20a_semaphore_pool { struct list_head hw_semas; /* List of HW semas. */ DECLARE_BITMAP(semas_alloced, PAGE_SIZE / SEMAPHORE_SIZE); - struct gk20a_semaphore_sea *sema_sea; /* Sea that owns this pool. */ + struct nvgpu_semaphore_sea *sema_sea; /* Sea that owns this pool. */ struct mutex pool_lock; @@ -114,7 +114,7 @@ struct gk20a_semaphore_pool { * pool. Channels then allocate regular semaphores - basically just a value that * signifies when a particular job is done. */ -struct gk20a_semaphore_sea { +struct nvgpu_semaphore_sea { struct list_head pool_list; /* List of pools in this sea. */ struct gk20a *gk20a; @@ -149,33 +149,33 @@ struct gk20a_semaphore_sea { /* * Semaphore sea functions. */ -struct gk20a_semaphore_sea *gk20a_semaphore_sea_create(struct gk20a *gk20a); -int gk20a_semaphore_sea_map(struct gk20a_semaphore_pool *sea, +struct nvgpu_semaphore_sea *nvgpu_semaphore_sea_create(struct gk20a *gk20a); +int nvgpu_semaphore_sea_map(struct nvgpu_semaphore_pool *sea, struct vm_gk20a *vm); -void gk20a_semaphore_sea_unmap(struct gk20a_semaphore_pool *sea, +void nvgpu_semaphore_sea_unmap(struct nvgpu_semaphore_pool *sea, struct vm_gk20a *vm); -struct gk20a_semaphore_sea *gk20a_semaphore_get_sea(struct gk20a *g); +struct nvgpu_semaphore_sea *nvgpu_semaphore_get_sea(struct gk20a *g); /* * Semaphore pool functions. */ -struct gk20a_semaphore_pool *gk20a_semaphore_pool_alloc( - struct gk20a_semaphore_sea *sea); -int gk20a_semaphore_pool_map(struct gk20a_semaphore_pool *pool, +struct nvgpu_semaphore_pool *nvgpu_semaphore_pool_alloc( + struct nvgpu_semaphore_sea *sea); +int nvgpu_semaphore_pool_map(struct nvgpu_semaphore_pool *pool, struct vm_gk20a *vm); -void gk20a_semaphore_pool_unmap(struct gk20a_semaphore_pool *pool, +void nvgpu_semaphore_pool_unmap(struct nvgpu_semaphore_pool *pool, struct vm_gk20a *vm); -u64 __gk20a_semaphore_pool_gpu_va(struct gk20a_semaphore_pool *p, bool global); -void gk20a_semaphore_pool_get(struct gk20a_semaphore_pool *p); -void gk20a_semaphore_pool_put(struct gk20a_semaphore_pool *p); +u64 __nvgpu_semaphore_pool_gpu_va(struct nvgpu_semaphore_pool *p, bool global); +void nvgpu_semaphore_pool_get(struct nvgpu_semaphore_pool *p); +void nvgpu_semaphore_pool_put(struct nvgpu_semaphore_pool *p); /* * Semaphore functions. */ -struct gk20a_semaphore *gk20a_semaphore_alloc(struct channel_gk20a *ch); -void gk20a_semaphore_put(struct gk20a_semaphore *s); -void gk20a_semaphore_get(struct gk20a_semaphore *s); -void gk20a_semaphore_free_hw_sema(struct channel_gk20a *ch); +struct nvgpu_semaphore *nvgpu_semaphore_alloc(struct channel_gk20a *ch); +void nvgpu_semaphore_put(struct nvgpu_semaphore *s); +void nvgpu_semaphore_get(struct nvgpu_semaphore *s); +void nvgpu_semaphore_free_hw_sema(struct channel_gk20a *ch); /* * Return the address of a specific semaphore. @@ -183,9 +183,9 @@ void gk20a_semaphore_free_hw_sema(struct channel_gk20a *ch); * Don't call this on a semaphore you don't own - the VA returned will make no * sense in your specific channel's VM. */ -static inline u64 gk20a_semaphore_gpu_rw_va(struct gk20a_semaphore *s) +static inline u64 nvgpu_semaphore_gpu_rw_va(struct nvgpu_semaphore *s) { - return __gk20a_semaphore_pool_gpu_va(s->hw_sema->p, false) + + return __nvgpu_semaphore_pool_gpu_va(s->hw_sema->p, false) + s->hw_sema->offset; } @@ -193,22 +193,22 @@ static inline u64 gk20a_semaphore_gpu_rw_va(struct gk20a_semaphore *s) * Get the global RO address for the semaphore. Can be called on any semaphore * regardless of whether you own it. */ -static inline u64 gk20a_semaphore_gpu_ro_va(struct gk20a_semaphore *s) +static inline u64 nvgpu_semaphore_gpu_ro_va(struct nvgpu_semaphore *s) { - return __gk20a_semaphore_pool_gpu_va(s->hw_sema->p, true) + + return __nvgpu_semaphore_pool_gpu_va(s->hw_sema->p, true) + s->hw_sema->offset; } -static inline u64 gk20a_hw_sema_addr(struct gk20a_semaphore_int *hw_sema) +static inline u64 nvgpu_hw_sema_addr(struct nvgpu_semaphore_int *hw_sema) { - return __gk20a_semaphore_pool_gpu_va(hw_sema->p, true) + + return __nvgpu_semaphore_pool_gpu_va(hw_sema->p, true) + hw_sema->offset; } /* * TODO: handle wrap around... Hmm, how to do this? */ -static inline bool gk20a_semaphore_is_released(struct gk20a_semaphore *s) +static inline bool nvgpu_semaphore_is_released(struct nvgpu_semaphore *s) { u32 sema_val = readl(s->hw_sema->value); @@ -220,25 +220,25 @@ static inline bool gk20a_semaphore_is_released(struct gk20a_semaphore *s) return (int)sema_val >= atomic_read(&s->value); } -static inline bool gk20a_semaphore_is_acquired(struct gk20a_semaphore *s) +static inline bool nvgpu_semaphore_is_acquired(struct nvgpu_semaphore *s) { - return !gk20a_semaphore_is_released(s); + return !nvgpu_semaphore_is_released(s); } /* * Read the underlying value from a semaphore. */ -static inline u32 gk20a_semaphore_read(struct gk20a_semaphore *s) +static inline u32 nvgpu_semaphore_read(struct nvgpu_semaphore *s) { return readl(s->hw_sema->value); } -static inline u32 gk20a_semaphore_get_value(struct gk20a_semaphore *s) +static inline u32 nvgpu_semaphore_get_value(struct nvgpu_semaphore *s) { return (u32)atomic_read(&s->value); } -static inline u32 gk20a_semaphore_next_value(struct gk20a_semaphore *s) +static inline u32 nvgpu_semaphore_next_value(struct nvgpu_semaphore *s) { return (u32)atomic_read(&s->hw_sema->next_value); } @@ -247,11 +247,11 @@ static inline u32 gk20a_semaphore_next_value(struct gk20a_semaphore *s) * If @force is set then this will not wait for the underlying semaphore to * catch up to the passed semaphore. */ -static inline void __gk20a_semaphore_release(struct gk20a_semaphore *s, +static inline void __nvgpu_semaphore_release(struct nvgpu_semaphore *s, bool force) { u32 current_val; - u32 val = gk20a_semaphore_get_value(s); + u32 val = nvgpu_semaphore_get_value(s); int attempts = 0; /* @@ -260,7 +260,7 @@ static inline void __gk20a_semaphore_release(struct gk20a_semaphore *s, * * TODO: tune the wait a little better. */ - while ((current_val = gk20a_semaphore_read(s)) < (val - 1)) { + while ((current_val = nvgpu_semaphore_read(s)) < (val - 1)) { if (force) break; msleep(100); @@ -284,21 +284,21 @@ static inline void __gk20a_semaphore_release(struct gk20a_semaphore *s, s->hw_sema->ch->hw_chid, val); } -static inline void gk20a_semaphore_release(struct gk20a_semaphore *s) +static inline void nvgpu_semaphore_release(struct nvgpu_semaphore *s) { - __gk20a_semaphore_release(s, false); + __nvgpu_semaphore_release(s, false); } /* * Configure a software based increment on this semaphore. This is useful for * when we want the GPU to wait on a SW event before processing a channel. * Another way to describe this is when the GPU needs to wait on a SW pre-fence. - * The pre-fence signals SW which in turn calls gk20a_semaphore_release() which + * The pre-fence signals SW which in turn calls nvgpu_semaphore_release() which * then allows the GPU to continue. * * Also used to prep a semaphore for an INCR by the GPU. */ -static inline void gk20a_semaphore_incr(struct gk20a_semaphore *s) +static inline void nvgpu_semaphore_incr(struct nvgpu_semaphore *s) { BUG_ON(s->incremented); @@ -307,6 +307,6 @@ static inline void gk20a_semaphore_incr(struct gk20a_semaphore *s) gpu_sema_verbose_dbg("INCR sema for c=%d (%u)", s->hw_sema->ch->hw_chid, - gk20a_semaphore_next_value(s)); + nvgpu_semaphore_next_value(s)); } #endif -- cgit v1.2.2