From e62785190f74cfbf9003a190a768e9077373bf6f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Aug 2018 08:28:23 -0700 Subject: gpu: nvgpu: Move priv_ring HAL to common Move implementation of priv_ring HAL to common/priv_ring. Implement two new HAL APIs to remove illegal dependencies: enable_priv_ring and enum_ltc. As enum_ltc can be implemented only gm20b onwards, bump gk20a implementation to base on gm20b. JIRA NVGPU-964 Change-Id: I160c2216132aadbcd98bb4a688aeeb2c520a9bc0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1797025 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 4 +- drivers/gpu/nvgpu/Makefile.sources | 4 +- .../gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c | 121 +++++++++++++ .../gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h | 32 ++++ .../gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c | 198 ++++++++++++++++++++ .../gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h | 33 ++++ drivers/gpu/nvgpu/gk20a/gk20a.c | 2 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 +- drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 119 ------------ drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h | 33 ---- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 8 +- drivers/gpu/nvgpu/gp106/hal_gp106.c | 8 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 7 +- drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | 199 --------------------- drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h | 33 ---- drivers/gpu/nvgpu/gv100/hal_gv100.c | 7 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 +- drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | 3 +- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 7 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 7 +- 20 files changed, 427 insertions(+), 408 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c create mode 100644 drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h create mode 100644 drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c create mode 100644 drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c delete mode 100644 drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h delete mode 100644 drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 6a075ce4..8c289947 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -27,6 +27,8 @@ nvgpu-y += common/bus/bus_gk20a.o \ common/bus/bus_gm20b.o \ common/bus/bus_gp10b.o \ common/bus/bus_gv100.o \ + common/priv_ring/priv_ring_gm20b.o \ + common/priv_ring/priv_ring_gp10b.o \ common/ptimer/ptimer.o \ common/ptimer/ptimer_gk20a.o \ common/fb/fb_gk20a.o \ @@ -201,7 +203,6 @@ nvgpu-y += \ gk20a/mm_gk20a.o \ gk20a/pmu_gk20a.o \ gk20a/flcn_gk20a.o \ - gk20a/priv_ring_gk20a.o \ gk20a/fence_gk20a.o \ gk20a/therm_gk20a.o \ gk20a/gr_ctx_gk20a_sim.o \ @@ -269,7 +270,6 @@ nvgpu-y += \ gp10b/regops_gp10b.o \ gp10b/therm_gp10b.o \ gp10b/fecs_trace_gp10b.o \ - gp10b/priv_ring_gp10b.o \ gp10b/gp10b.o \ gp10b/fuse_gp10b.o \ gp10b/ecc_gp10b.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 677b20bd..e8e107ae 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -36,6 +36,8 @@ srcs := common/mm/nvgpu_allocator.c \ common/bus/bus_gm20b.c \ common/bus/bus_gp10b.c \ common/bus/bus_gv100.c \ + common/priv_ring/priv_ring_gm20b.c \ + common/priv_ring/priv_ring_gp10b.c \ common/fb/fb_gk20a.c \ common/fb/fb_gm20b.c \ common/fb/fb_gp10b.c \ @@ -135,7 +137,6 @@ srcs := common/mm/nvgpu_allocator.c \ gk20a/mm_gk20a.c \ gk20a/pmu_gk20a.c \ gk20a/flcn_gk20a.c \ - gk20a/priv_ring_gk20a.c \ gk20a/fence_gk20a.c \ gk20a/therm_gk20a.c \ gk20a/gr_ctx_gk20a_sim.c \ @@ -167,7 +168,6 @@ srcs := common/mm/nvgpu_allocator.c \ gp10b/regops_gp10b.c \ gp10b/therm_gp10b.c \ gp10b/fecs_trace_gp10b.c \ - gp10b/priv_ring_gp10b.c \ gp10b/gp10b.c \ gp10b/fuse_gp10b.c \ gp10b/ecc_gp10b.c \ diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c new file mode 100644 index 00000000..1445473a --- /dev/null +++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +#include +#include +#include +#include +#include + +#include "priv_ring_gm20b.h" + +#include +#include +#include + +void gm20b_priv_ring_enable(struct gk20a *g) +{ + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) + return; + + nvgpu_log(g, gpu_dbg_info, "enabling priv ring"); + + if (g->ops.clock_gating.slcg_priring_load_gating_prod) + g->ops.clock_gating.slcg_priring_load_gating_prod(g, + g->slcg_enabled); + + gk20a_writel(g,pri_ringmaster_command_r(), + 0x4); + + gk20a_writel(g, pri_ringstation_sys_decode_config_r(), + 0x2); + gk20a_readl(g, pri_ringstation_sys_decode_config_r()); +} + +void gm20b_priv_ring_isr(struct gk20a *g) +{ + u32 status0, status1; + u32 cmd; + s32 retry = 100; + u32 gpc; + u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) + return; + + status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); + status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); + + nvgpu_log(g, gpu_dbg_intr, "ringmaster intr status0: 0x%08x," + "status1: 0x%08x", status0, status1); + + if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { + nvgpu_log(g, gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", + gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_code_r())); + } + + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + if (status1 & BIT(gpc)) { + nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride), + gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride)); + } + } + /* clear interrupt */ + cmd = gk20a_readl(g, pri_ringmaster_command_r()); + cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), + pri_ringmaster_command_cmd_ack_interrupt_f()); + gk20a_writel(g, pri_ringmaster_command_r(), cmd); + /* poll for clear interrupt done */ + cmd = pri_ringmaster_command_cmd_v( + gk20a_readl(g, pri_ringmaster_command_r())); + while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) { + nvgpu_udelay(20); + retry--; + cmd = pri_ringmaster_command_cmd_v( + gk20a_readl(g, pri_ringmaster_command_r())); + } + if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) + nvgpu_warn(g, "priv ringmaster intr ack too many retries"); +} + +void gm20b_priv_set_timeout_settings(struct gk20a *g) +{ + /* + * Bug 1340570: increase the clock timeout to avoid potential + * operation failure at high gpcclk rate. Default values are 0x400. + */ + nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); + nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); +} + +u32 gm20b_priv_ring_enum_ltc(struct gk20a *g) +{ + return gk20a_readl(g, pri_ringmaster_enum_ltc_r()); +} diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h new file mode 100644 index 00000000..02f20515 --- /dev/null +++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gm20b.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __PRIV_RING_GM20B_H__ +#define __PRIV_RING_GM20B_H__ + +struct gk20a; + +void gm20b_priv_ring_isr(struct gk20a *g); +void gm20b_priv_ring_enable(struct gk20a *g); +void gm20b_priv_set_timeout_settings(struct gk20a *g); +u32 gm20b_priv_ring_enum_ltc(struct gk20a *g); + +#endif /*__PRIV_RING_GM20B_H__*/ diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c new file mode 100644 index 00000000..04525375 --- /dev/null +++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.c @@ -0,0 +1,198 @@ +/* + * GP10B priv ring + * + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include "gk20a/gk20a.h" + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "priv_ring_gp10b.h" + +static const char *const error_type_badf1xyy[] = { + "client timeout", + "decode error", + "client in reset", + "client floorswept", + "client stuck ack", + "client expected ack", + "fence error", + "subid error", + "byte access unsupported", +}; + +static const char *const error_type_badf2xyy[] = { + "orphan gpc/fbp" +}; + +static const char *const error_type_badf3xyy[] = { + "priv ring dead" +}; + +static const char *const error_type_badf5xyy[] = { + "client error", + "priv level violation", + "indirect priv level violation", + "local local ring error", + "falcon mem access priv level violation", + "pri route error" +}; + +void gp10b_priv_ring_decode_error_code(struct gk20a *g, + u32 error_code) +{ + u32 error_type_index; + + error_type_index = (error_code & 0x00000f00) >> 16; + error_code = error_code & 0xBADFf000; + + if (error_code == 0xBADF1000) { + if (error_type_index < + ARRAY_SIZE(error_type_badf1xyy)) + nvgpu_err(g, "%s", + error_type_badf1xyy[error_type_index]); + } else if (error_code == 0xBADF2000) { + if (error_type_index < + ARRAY_SIZE(error_type_badf2xyy)) + nvgpu_err(g, "%s", + error_type_badf2xyy[error_type_index]); + } else if (error_code == 0xBADF3000) { + if (error_type_index < + ARRAY_SIZE(error_type_badf3xyy)) + nvgpu_err(g, "%s", + error_type_badf3xyy[error_type_index]); + } else if (error_code == 0xBADF5000) { + if (error_type_index < + ARRAY_SIZE(error_type_badf5xyy)) + nvgpu_err(g, "%s", + error_type_badf5xyy[error_type_index]); + } +} + +void gp10b_priv_ring_isr(struct gk20a *g) +{ + u32 status0, status1; + u32 cmd; + s32 retry = 100; + u32 gpc; + u32 gpc_stride, offset; + u32 error_info; + u32 error_code; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + nvgpu_info(g, "unhandled priv ring intr"); + return; + } + + status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); + status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); + + nvgpu_err(g, "ringmaster intr status0: 0x%08x," + "status1: 0x%08x", status0, status1); + + if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0) + nvgpu_err(g, + "BUG: connectivity problem on the startup sequence"); + + if (pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0) + nvgpu_err(g, "ring disconnected"); + + if (pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) + nvgpu_err(g, "ring overflowed"); + + if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { + error_info = + gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()); + error_code = + gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()); + nvgpu_err(g, "SYS write error. ADR 0x%08x WRDAT 0x%08x " + "INFO 0x%08x (subid 0x%08x priv level %d), " + "CODE 0x%08x", + gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), + gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), + error_info, + pri_ringstation_sys_priv_error_info_subid_v(error_info), + pri_ringstation_sys_priv_error_info_priv_level_v(error_info), + error_code); + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, error_code); + } + + if (status1) { + gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + offset = gpc * gpc_stride; + if (status1 & BIT(gpc)) { + error_info = gk20a_readl(g, + pri_ringstation_gpc_gpc0_priv_error_info_r() + offset); + error_code = gk20a_readl(g, + pri_ringstation_gpc_gpc0_priv_error_code_r() + offset); + nvgpu_err(g, "GPC%u write error. ADR 0x%08x " + "WRDAT 0x%08x " + "INFO 0x%08x (subid 0x%08x priv level %d), " + "CODE 0x%08x", gpc, + gk20a_readl(g, + pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset), + gk20a_readl(g, + pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset), + error_info, + pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info), + pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), + error_code); + + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, + error_code); + + status1 = status1 & (~(BIT(gpc))); + if (!status1) + break; + } + } + } + /* clear interrupt */ + cmd = gk20a_readl(g, pri_ringmaster_command_r()); + cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), + pri_ringmaster_command_cmd_ack_interrupt_f()); + gk20a_writel(g, pri_ringmaster_command_r(), cmd); + + /* poll for clear interrupt done */ + cmd = pri_ringmaster_command_cmd_v( + gk20a_readl(g, pri_ringmaster_command_r())); + while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) { + nvgpu_udelay(20); + cmd = pri_ringmaster_command_cmd_v( + gk20a_readl(g, pri_ringmaster_command_r())); + retry--; + } + + if (retry == 0) + nvgpu_err(g, "priv ringmaster intr ack failed"); +} diff --git a/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h new file mode 100644 index 00000000..dd418e5b --- /dev/null +++ b/drivers/gpu/nvgpu/common/priv_ring/priv_ring_gp10b.h @@ -0,0 +1,33 @@ +/* + * GP10B PRIV ringmaster + * + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef __PRIV_RING_GP10B_H__ +#define __PRIV_RING_GP10B_H__ + +struct gk20a; + +void gp10b_priv_ring_isr(struct gk20a *g); +void gp10b_priv_ring_decode_error_code(struct gk20a *g, + u32 error_code); + +#endif /*__PRIV_RING_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 7fec4da7..24cfc6ec 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -187,7 +187,7 @@ int gk20a_finalize_poweron(struct gk20a *g) if (g->ops.clk.disable_slowboot) g->ops.clk.disable_slowboot(g); - gk20a_enable_priv_ring(g); + g->ops.priv_ring.enable_priv_ring(g); /* TBD: move this after graphics init in which blcg/slcg is enabled. This function removes SlowdownOnBoot which applies 32x divider diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index bd477208..c29c03f0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter; #include "fifo_gk20a.h" #include "tsg_gk20a.h" #include "pmu_gk20a.h" -#include "priv_ring_gk20a.h" #include "therm_gk20a.h" #include "clk/clk.h" #include "perf/perf.h" @@ -1235,9 +1234,11 @@ struct gpu_ops { void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); } falcon; struct { + void (*enable_priv_ring)(struct gk20a *g); void (*isr)(struct gk20a *g); void (*decode_error_code)(struct gk20a *g, u32 error_code); void (*set_ppriv_timeout_settings)(struct gk20a *g); + u32 (*enum_ltc)(struct gk20a *g); } priv_ring; struct { int (*check_priv_security)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c deleted file mode 100644 index 0e004a5d..00000000 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * GK20A priv ring - * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a.h" - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -void gk20a_enable_priv_ring(struct gk20a *g) -{ - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) - return; - - nvgpu_log(g, gpu_dbg_info, "enabling priv ring"); - - if (g->ops.clock_gating.slcg_priring_load_gating_prod) - g->ops.clock_gating.slcg_priring_load_gating_prod(g, - g->slcg_enabled); - - gk20a_writel(g,pri_ringmaster_command_r(), - 0x4); - - gk20a_writel(g, pri_ringstation_sys_decode_config_r(), - 0x2); - gk20a_readl(g, pri_ringstation_sys_decode_config_r()); -} - -void gk20a_priv_ring_isr(struct gk20a *g) -{ - u32 status0, status1; - u32 cmd; - s32 retry = 100; - u32 gpc; - u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); - - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) - return; - - status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); - status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); - - nvgpu_log(g, gpu_dbg_intr, "ringmaster intr status0: 0x%08x," - "status1: 0x%08x", status0, status1); - - if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { - nvgpu_log(g, gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", - gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_code_r())); - } - - for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { - if (status1 & BIT(gpc)) { - nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc, - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride), - gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride)); - } - } - /* clear interrupt */ - cmd = gk20a_readl(g, pri_ringmaster_command_r()); - cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), - pri_ringmaster_command_cmd_ack_interrupt_f()); - gk20a_writel(g, pri_ringmaster_command_r(), cmd); - /* poll for clear interrupt done */ - cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); - while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) { - nvgpu_udelay(20); - retry--; - cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); - } - if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) - nvgpu_warn(g, "priv ringmaster intr ack too many retries"); -} - -void gk20a_priv_set_timeout_settings(struct gk20a *g) -{ - /* - * Bug 1340570: increase the clock timeout to avoid potential - * operation failure at high gpcclk rate. Default values are 0x400. - */ - nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); - nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); - nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800); -} diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h deleted file mode 100644 index 98040624..00000000 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * GK20A PRIV ringmaster - * - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __PRIV_RING_GK20A_H__ -#define __PRIV_RING_GK20A_H__ - -struct gpu_ops; - -void gk20a_priv_ring_isr(struct gk20a *g); -void gk20a_enable_priv_ring(struct gk20a *g); -void gk20a_priv_set_timeout_settings(struct gk20a *g); - -#endif /*__PRIV_RING_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index b37f6244..e6c4c8d1 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -25,6 +25,7 @@ #include "common/clock_gating/gm20b_gating_reglist.h" #include "common/bus/bus_gm20b.h" #include "common/bus/bus_gk20a.h" +#include "common/priv_ring/priv_ring_gm20b.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -38,7 +39,6 @@ #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/flcn_gk20a.h" -#include "gk20a/priv_ring_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/pmu_gk20a.h" #include "gk20a/gr_gk20a.h" @@ -641,9 +641,11 @@ static const struct gpu_ops gm20b_ops = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .priv_ring = { - .isr = gk20a_priv_ring_isr, + .enable_priv_ring = gm20b_priv_ring_enable, + .isr = gm20b_priv_ring_isr, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .check_priv_security = gm20b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index a2e76a00..90d25fa0 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -27,6 +27,8 @@ #include "common/ptimer/ptimer_gk20a.h" #include "common/bus/bus_gm20b.h" #include "common/bus/bus_gp10b.h" +#include "common/priv_ring/priv_ring_gm20b.h" +#include "common/priv_ring/priv_ring_gp10b.h" #include "common/fb/fb_gk20a.h" #include "common/fb/fb_gp10b.h" #include "common/fb/fb_gm20b.h" @@ -52,11 +54,9 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/regops_gp10b.h" -#include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_gp10b.h" -#include "gp10b/priv_ring_gp10b.h" #include "gp10b/fuse_gp10b.h" #include "gp106/fifo_gp106.h" @@ -774,10 +774,12 @@ static const struct gpu_ops gp106_ops = { .falcon_hal_sw_init = gp106_falcon_hal_sw_init, }, .priv_ring = { + .enable_priv_ring = gm20b_priv_ring_enable, .isr = gp10b_priv_ring_isr, .decode_error_code = gp10b_priv_ring_decode_error_code, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .check_priv_security = gp106_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 3d5eb231..5f55baa3 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -27,6 +27,8 @@ #include "common/ptimer/ptimer_gk20a.h" #include "common/bus/bus_gm20b.h" #include "common/bus/bus_gp10b.h" +#include "common/priv_ring/priv_ring_gm20b.h" +#include "common/priv_ring/priv_ring_gp10b.h" #include "common/fb/fb_gk20a.h" #include "common/fb/fb_gm20b.h" #include "common/fb/fb_gp10b.h" @@ -55,7 +57,6 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/regops_gp10b.h" #include "gp10b/therm_gp10b.h" -#include "gp10b/priv_ring_gp10b.h" #include "gp10b/ecc_gp10b.h" #include "gm20b/ltc_gm20b.h" @@ -687,10 +688,12 @@ static const struct gpu_ops gp10b_ops = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .priv_ring = { + .enable_priv_ring = gm20b_priv_ring_enable, .isr = gp10b_priv_ring_isr, .decode_error_code = gp10b_priv_ring_decode_error_code, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c deleted file mode 100644 index 9fcf060b..00000000 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * GP10B priv ring - * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include "gk20a/gk20a.h" - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "priv_ring_gp10b.h" - -static const char *const error_type_badf1xyy[] = { - "client timeout", - "decode error", - "client in reset", - "client floorswept", - "client stuck ack", - "client expected ack", - "fence error", - "subid error", - "byte access unsupported", -}; - -static const char *const error_type_badf2xyy[] = { - "orphan gpc/fbp" -}; - -static const char *const error_type_badf3xyy[] = { - "priv ring dead" -}; - -static const char *const error_type_badf5xyy[] = { - "client error", - "priv level violation", - "indirect priv level violation", - "local local ring error", - "falcon mem access priv level violation", - "pri route error" -}; - -void gp10b_priv_ring_decode_error_code(struct gk20a *g, - u32 error_code) -{ - u32 error_type_index; - - error_type_index = (error_code & 0x00000f00) >> 16; - error_code = error_code & 0xBADFf000; - - if (error_code == 0xBADF1000) { - if (error_type_index < - ARRAY_SIZE(error_type_badf1xyy)) - nvgpu_err(g, "%s", - error_type_badf1xyy[error_type_index]); - } else if (error_code == 0xBADF2000) { - if (error_type_index < - ARRAY_SIZE(error_type_badf2xyy)) - nvgpu_err(g, "%s", - error_type_badf2xyy[error_type_index]); - } else if (error_code == 0xBADF3000) { - if (error_type_index < - ARRAY_SIZE(error_type_badf3xyy)) - nvgpu_err(g, "%s", - error_type_badf3xyy[error_type_index]); - } else if (error_code == 0xBADF5000) { - if (error_type_index < - ARRAY_SIZE(error_type_badf5xyy)) - nvgpu_err(g, "%s", - error_type_badf5xyy[error_type_index]); - } -} - -void gp10b_priv_ring_isr(struct gk20a *g) -{ - u32 status0, status1; - u32 cmd; - s32 retry = 100; - u32 gpc; - u32 gpc_stride, offset; - u32 error_info; - u32 error_code; - - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - nvgpu_info(g, "unhandled priv ring intr"); - return; - } - - status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); - status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); - - nvgpu_err(g, "ringmaster intr status0: 0x%08x," - "status1: 0x%08x", status0, status1); - - if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0) - nvgpu_err(g, - "BUG: connectivity problem on the startup sequence"); - - if (pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0) - nvgpu_err(g, "ring disconnected"); - - if (pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) - nvgpu_err(g, "ring overflowed"); - - if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) { - error_info = - gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()); - error_code = - gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()); - nvgpu_err(g, "SYS write error. ADR 0x%08x WRDAT 0x%08x " - "INFO 0x%08x (subid 0x%08x priv level %d), " - "CODE 0x%08x", - gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()), - gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()), - error_info, - pri_ringstation_sys_priv_error_info_subid_v(error_info), - pri_ringstation_sys_priv_error_info_priv_level_v(error_info), - error_code); - if (g->ops.priv_ring.decode_error_code) - g->ops.priv_ring.decode_error_code(g, error_code); - } - - if (status1) { - gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE); - for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { - offset = gpc * gpc_stride; - if (status1 & BIT(gpc)) { - error_info = gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_info_r() + offset); - error_code = gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_code_r() + offset); - nvgpu_err(g, "GPC%u write error. ADR 0x%08x " - "WRDAT 0x%08x " - "INFO 0x%08x (subid 0x%08x priv level %d), " - "CODE 0x%08x", gpc, - gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_adr_r() + offset), - gk20a_readl(g, - pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + offset), - error_info, - pri_ringstation_gpc_gpc0_priv_error_info_subid_v(error_info), - pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), - error_code); - - if (g->ops.priv_ring.decode_error_code) - g->ops.priv_ring.decode_error_code(g, - error_code); - - status1 = status1 & (~(BIT(gpc))); - if (!status1) - break; - } - } - } - /* clear interrupt */ - cmd = gk20a_readl(g, pri_ringmaster_command_r()); - cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), - pri_ringmaster_command_cmd_ack_interrupt_f()); - gk20a_writel(g, pri_ringmaster_command_r(), cmd); - - /* poll for clear interrupt done */ - cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); - while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) { - nvgpu_udelay(20); - cmd = pri_ringmaster_command_cmd_v( - gk20a_readl(g, pri_ringmaster_command_r())); - retry--; - } - - if (retry == 0) - nvgpu_err(g, "priv ringmaster intr ack failed"); -} diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h deleted file mode 100644 index dd418e5b..00000000 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * GP10B PRIV ringmaster - * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef __PRIV_RING_GP10B_H__ -#define __PRIV_RING_GP10B_H__ - -struct gk20a; - -void gp10b_priv_ring_isr(struct gk20a *g); -void gp10b_priv_ring_decode_error_code(struct gk20a *g, - u32 error_code); - -#endif /*__PRIV_RING_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f6c3ec67..344ad1e8 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -25,6 +25,8 @@ #include "common/bus/bus_gk20a.h" #include "common/bus/bus_gp10b.h" #include "common/bus/bus_gv100.h" +#include "common/priv_ring/priv_ring_gm20b.h" +#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gv100_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gk20a.h" @@ -68,7 +70,6 @@ #include "gp10b/therm_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ce_gp10b.h" -#include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mm_gp10b.h" @@ -868,10 +869,12 @@ static const struct gpu_ops gv100_ops = { .falcon_hal_sw_init = gv100_falcon_hal_sw_init, }, .priv_ring = { + .enable_priv_ring = gm20b_priv_ring_enable, .isr = gp10b_priv_ring_isr, .decode_error_code = gp10b_priv_ring_decode_error_code, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 20a0b34f..05763cce 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,8 @@ #include "common/bus/bus_gk20a.h" #include "common/bus/bus_gp10b.h" #include "common/bus/bus_gm20b.h" +#include "common/priv_ring/priv_ring_gm20b.h" +#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gv11b_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/fb/fb_gk20a.h" @@ -55,7 +57,6 @@ #include "gp10b/therm_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ce_gp10b.h" -#include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mm_gp10b.h" @@ -786,10 +787,12 @@ static const struct gpu_ops gv11b_ops = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .priv_ring = { + .enable_priv_ring = gm20b_priv_ring_enable, .isr = gp10b_priv_ring_isr, .decode_error_code = gp10b_priv_ring_decode_error_code, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 32f72208..d7c385a9 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c @@ -32,7 +32,6 @@ #include #include #include -#include #include @@ -62,7 +61,7 @@ void gv11b_ltc_init_fs_state(struct gk20a *g) nvgpu_log_info(g, "initialize gv11b l2"); g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); - g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); + g->ltc_count = g->ops.priv_ring.enum_ltc(g); nvgpu_log_info(g, "%u ltcs out of %u", g->ltc_count, g->max_ltc_count); reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index a8aa023b..15e2717d 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -22,6 +22,8 @@ #include "common/bus/bus_gk20a.h" #include "common/bus/bus_gm20b.h" +#include "common/priv_ring/priv_ring_gm20b.h" +#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gp10b_gating_reglist.h" #include "common/fb/fb_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -55,7 +57,6 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/regops_gp10b.h" #include "gp10b/therm_gp10b.h" -#include "gp10b/priv_ring_gp10b.h" #include "gp10b/fuse_gp10b.h" #include "gm20b/ltc_gm20b.h" @@ -552,9 +553,11 @@ static const struct gpu_ops vgpu_gp10b_ops = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .priv_ring = { + .enable_priv_ring = gm20b_priv_ring_enable, .isr = gp10b_priv_ring_isr, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .check_priv_security = vgpu_gp10b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index b91691e2..995a2c2c 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -22,6 +22,8 @@ #include "common/bus/bus_gk20a.h" #include "common/bus/bus_gm20b.h" +#include "common/priv_ring/priv_ring_gm20b.h" +#include "common/priv_ring/priv_ring_gp10b.h" #include "common/clock_gating/gv11b_gating_reglist.h" #include "common/fb/fb_gk20a.h" #include "common/fb/fb_gm20b.h" @@ -62,7 +64,6 @@ #include "gp10b/gr_gp10b.h" #include #include -#include #include #include @@ -622,9 +623,11 @@ static const struct gpu_ops vgpu_gv11b_ops = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, .priv_ring = { + .enable_priv_ring = gm20b_priv_ring_enable, .isr = gp10b_priv_ring_isr, .set_ppriv_timeout_settings = - gk20a_priv_set_timeout_settings, + gm20b_priv_set_timeout_settings, + .enum_ltc = gm20b_priv_ring_enum_ltc, }, .fuse = { .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, -- cgit v1.2.2