From e1c4d19b4cd2462c2f5b8c6653573ea0e6bbe823 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 21 Mar 2017 09:57:25 -0700 Subject: gpu: nvgpu: add and reorg reset_enable_hw fifo ops fifo reset_enable_hw is reorged to clear and enable pbdma/fifo interrupts after all the required configuration such as configuring timeouts, enabling timeout detections are taken care of. JIRA GPUT19X-74 JIRA GPUT19X-47 Change-Id: Id780cc11d858db18f8d748c037954ede73298506 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1325351 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 62 +++++++++++++++++++----------------- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 ++ drivers/gpu/nvgpu/gk20a/gk20a.c | 3 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 + 5 files changed, 38 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 6c4f12df..35a07439 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -726,8 +726,6 @@ clean_up_runlist: return -ENOMEM; } -#define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 - u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g) { u32 intr_0_error_mask = @@ -765,6 +763,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); gk20a_dbg_fn(""); + /* enable pmc pfifo */ g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); @@ -784,36 +783,10 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); gk20a_writel(g, mc_enable_pb_r(), mask); - /* enable pfifo interrupt */ - gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); - gk20a_writel(g, fifo_intr_en_0_r(), gk20a_fifo_intr_0_en_mask(g)); - gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); - - /* enable pbdma interrupt */ - mask = 0; - for (i = 0; i < host_num_pbdma; i++) { - intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); - intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f(); - gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); - gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); - gk20a_writel(g, pbdma_intr_en_0_r(i), - ~pbdma_intr_en_0_lbreq_enabled_f()); - gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); - gk20a_writel(g, pbdma_intr_en_1_r(i), - ~pbdma_intr_en_0_lbreq_enabled_f()); - } - - /* TBD: apply overrides */ - - /* TBD: BLCG prod */ - - /* reset runlist interrupts */ - gk20a_writel(g, fifo_intr_runlist_r(), ~0); - - /* TBD: do we need those? */ timeout = gk20a_readl(g, fifo_fb_timeout_r()); timeout = set_field(timeout, fifo_fb_timeout_period_m(), fifo_fb_timeout_period_max_f()); + gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); gk20a_writel(g, fifo_fb_timeout_r(), timeout); /* write pbdma timeout value */ @@ -821,9 +794,9 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) timeout = gk20a_readl(g, pbdma_timeout_r(i)); timeout = set_field(timeout, pbdma_timeout_period_m(), pbdma_timeout_period_max_f()); + gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); gk20a_writel(g, pbdma_timeout_r(i), timeout); } - if (g->ops.fifo.apply_pb_timeout) g->ops.fifo.apply_pb_timeout(g); @@ -833,6 +806,34 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) timeout |= fifo_eng_timeout_detection_enabled_f(); gk20a_writel(g, fifo_eng_timeout_r(), timeout); + /* clear and enable pbdma interrupt */ + for (i = 0; i < host_num_pbdma; i++) { + gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); + gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); + + intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); + intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f(); + gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); + gk20a_dbg_info("pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); + gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); + + gk20a_dbg_info("pbdma id:%u, intr_en_1 0x%08x", i, + ~pbdma_intr_en_0_lbreq_enabled_f()); + gk20a_writel(g, pbdma_intr_en_1_r(i), + ~pbdma_intr_en_0_lbreq_enabled_f()); + } + + /* reset runlist interrupts */ + gk20a_writel(g, fifo_intr_runlist_r(), ~0); + + /* clear and enable pfifo interrupt */ + gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); + mask = gk20a_fifo_intr_0_en_mask(g); + gk20a_dbg_info("fifo_intr_en_0 0x%08x", mask); + gk20a_writel(g, fifo_intr_en_0_r(), mask); + gk20a_dbg_info("fifo_intr_en_1 = 0x80000000"); + gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); + gk20a_dbg_fn("done"); return 0; @@ -3881,4 +3882,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; gops->fifo.init_pbdma_intr_descs = gk20a_fifo_init_pbdma_intr_descs; + gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; } diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index ae728a36..a9703385 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -38,6 +38,8 @@ #define PREEMPT_TIMEOUT_RC 1 #define PREEMPT_TIMEOUT_NORC 0 +#define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 + /* * Number of entries in the kickoff latency buffer, used to calculate * the profiling and histogram. This number is calculated to be statistically diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index e77986be..b715e661 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -567,7 +567,8 @@ int gk20a_pm_finalize_poweron(struct device *dev) } } - err = gk20a_init_fifo_reset_enable_hw(g); + err = g->ops.fifo.reset_enable_hw(g); + if (err) { gk20a_err(dev, "failed to reset gk20a fifo"); goto done; diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4e1c4ff4..ce26125d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -456,6 +456,7 @@ struct gpu_ops { int (*preempt_ch_tsg)(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type); void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); + int (*reset_enable_hw)(struct gk20a *g); } fifo; struct pmu_v { /*used for change of enum zbc update cmd id from ver 0 to ver1*/ diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 5a0bd39e..f09da825 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -223,4 +223,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs; + gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; } -- cgit v1.2.2