From e0587aaf4d8f803004365eef2b08c0becd1042cb Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 17:19:51 -0700 Subject: gpu: nvgpu: set FB/HSMMU debug mode Set NV_PFB_HSMMU_PRI_MMU_DEBUG_CTRL and NV_PFB_PRI_MMU_DEBUG_CTRL in addition to NV_PGRAPH_PRI_GPCS_MMU_DEBUG_CTRL, in NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE Bug 2515097 Bug 2713590 Change-Id: I1763b43e79fac3edb68a35980683d58bfa89519f Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2115785 (cherry picked from commit 8057514a9f7fc5f175e2e0571dfa91d78ebb6410) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208771 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka Reviewed-by: Alex Waterman Reviewed-by: Winnie Hsu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fb/fb_gm20b.c | 13 +++++++---- drivers/gpu/nvgpu/common/fb/fb_gm20b.h | 3 ++- drivers/gpu/nvgpu/common/fb/fb_gv100.c | 26 ++++++++++++++++++++- drivers/gpu/nvgpu/common/fb/fb_gv100.h | 3 ++- drivers/gpu/nvgpu/common/fifo/tsg.c | 33 +++++++++++++++++++-------- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 ++ drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 3 ++- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 + 12 files changed, 71 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c index f62bf9df..739274c5 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B GPC MMU * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -311,7 +311,7 @@ bool gm20b_fb_debug_mode_enabled(struct gk20a *g) fb_mmu_debug_ctrl_debug_enabled_v(); } -void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) +void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable) { u32 reg_val, fb_debug_ctrl; @@ -323,10 +323,15 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) g->mmu_debug_ctrl = false; } - reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); + reg_val = nvgpu_readl(g, fb_mmu_debug_ctrl_r()); reg_val = set_field(reg_val, fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); - gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); + nvgpu_writel(g, fb_mmu_debug_ctrl_r(), reg_val); +} +void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) +{ + gm20b_fb_set_mmu_debug_mode(g, enable); g->ops.gr.set_debug_mode(g, enable); } + diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h index d69f8618..aed9b43e 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B FB * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -49,5 +49,6 @@ void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); int gm20b_fb_vpr_info_fetch(struct gk20a *g); bool gm20b_fb_debug_mode_enabled(struct gk20a *g); void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable); +void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable); #endif diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index 193cf2f0..508259e7 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c @@ -1,7 +1,7 @@ /* * GV100 FB * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -300,3 +300,27 @@ size_t gv100_fb_get_vidmem_size(struct gk20a *g) return bytes; } + +void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable) +{ + u32 data, fb_ctrl, hsmmu_ctrl; + + if (enable) { + fb_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); + hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_enabled_f(); + g->mmu_debug_ctrl = true; + } else { + fb_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); + hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_disabled_f(); + g->mmu_debug_ctrl = false; + } + + data = nvgpu_readl(g, fb_mmu_debug_ctrl_r()); + data = set_field(data, fb_mmu_debug_ctrl_debug_m(), fb_ctrl); + nvgpu_writel(g, fb_mmu_debug_ctrl_r(), data); + + data = nvgpu_readl(g, fb_hsmmu_pri_mmu_debug_ctrl_r()); + data = set_field(data, + fb_hsmmu_pri_mmu_debug_ctrl_debug_m(), hsmmu_ctrl); + nvgpu_writel(g, fb_hsmmu_pri_mmu_debug_ctrl_r(), data); +} diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.h b/drivers/gpu/nvgpu/common/fb/fb_gv100.h index 161d4cd7..b83f664a 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.h +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.h @@ -1,7 +1,7 @@ /* * GV100 FB * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -34,5 +34,6 @@ int gv100_fb_memory_unlock(struct gk20a *g); int gv100_fb_init_nvlink(struct gk20a *g); int gv100_fb_enable_nvlink(struct gk20a *g); size_t gv100_fb_get_vidmem_size(struct gk20a *g); +void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable); #endif /* NVGPU_FB_GV100_H */ diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 5883667f..7f61b273 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c @@ -452,13 +452,15 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, struct gk20a *g; int err = 0; u32 tsg_refcnt; + u32 fb_refcnt; if ((ch == NULL) || (tsg == NULL)) { return -EINVAL; } g = ch->g; - if (g->ops.gr.set_mmu_debug_mode == NULL) { + if ((g->ops.fb.set_mmu_debug_mode == NULL) && + (g->ops.gr.set_mmu_debug_mode == NULL)) { return -ENOSYS; } @@ -468,26 +470,39 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, return 0; } tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; + fb_refcnt = g->mmu_debug_mode_refcnt + 1U; } else { if (!ch->mmu_debug_mode_enabled) { /* already disabled for this channel */ return 0; } tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; + fb_refcnt = g->mmu_debug_mode_refcnt - 1U; } - /* - * enable GPC MMU debug mode if it was requested for at - * least one channel in the TSG - */ - err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); - if (err != 0) { - nvgpu_err(g, "set mmu debug mode failed, err=%d", err); - return err; + if (g->ops.gr.set_mmu_debug_mode != NULL) { + /* + * enable GPC MMU debug mode if it was requested for at + * least one channel in the TSG + */ + err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); + if (err != 0) { + nvgpu_err(g, "set mmu debug mode failed, err=%d", err); + return err; + } + } + + if (g->ops.fb.set_mmu_debug_mode != NULL) { + /* + * enable FB/HS MMU debug mode if it was requested for + * at least one TSG + */ + g->ops.fb.set_mmu_debug_mode(g, fb_refcnt > 0U); } ch->mmu_debug_mode_enabled = enable; tsg->mmu_debug_mode_refcnt = tsg_refcnt; + g->mmu_debug_mode_refcnt = fb_refcnt; return err; } diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 0865ace4..9898c683 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -352,6 +352,7 @@ static const struct gpu_ops gm20b_ops = { .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, + .set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode, .tlb_invalidate = gm20b_fb_tlb_invalidate, .mem_unlock = NULL, }, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index eea40d5e..3cdba8ac 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -386,6 +386,7 @@ static const struct gpu_ops gp10b_ops = { .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, + .set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode, .tlb_invalidate = gm20b_fb_tlb_invalidate, .mem_unlock = NULL, }, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2e2c3b8f..f7fabf68 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -473,6 +473,7 @@ static const struct gpu_ops gv11b_ops = { .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, + .set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode, .tlb_invalidate = gm20b_fb_tlb_invalidate, .hub_isr = gv11b_fb_hub_isr, .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f3a83602..8b6de266 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -570,6 +570,7 @@ struct gpu_ops { struct wpr_carveout_info *inf); bool (*is_debug_mode_enabled)(struct gk20a *g); void (*set_debug_mode)(struct gk20a *g, bool enable); + void (*set_mmu_debug_mode)(struct gk20a *g, bool enable); int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); void (*hub_isr)(struct gk20a *g); void (*handle_replayable_fault)(struct gk20a *g); @@ -1623,6 +1624,7 @@ struct gk20a { struct gk20a_fecs_trace *fecs_trace; bool mmu_debug_ctrl; + u32 mmu_debug_mode_refcnt; u32 tpc_fs_mask_user; diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 408bbc64..aeed07ce 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -1091,7 +1091,8 @@ static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( return -EINVAL; } - if (g->ops.gr.set_mmu_debug_mode == NULL) { + if ((g->ops.fb.set_mmu_debug_mode == NULL) && + (g->ops.gr.set_mmu_debug_mode == NULL)) { return -ENOSYS; } diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 917ac638..a4f02faa 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -250,6 +250,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .read_wpr_info = NULL, .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, + .set_mmu_debug_mode = NULL, .tlb_invalidate = vgpu_mm_tlb_invalidate, }, .clock_gating = { diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 41850c91..f51d4c35 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -291,6 +291,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .read_wpr_info = NULL, .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, + .set_mmu_debug_mode = NULL, .tlb_invalidate = vgpu_mm_tlb_invalidate, .hub_isr = gv11b_fb_hub_isr, .enable_hub_intr = gv11b_fb_enable_hub_intr, -- cgit v1.2.2